[Bug target/119114] New: [14/15 regression] RISC-V: miscompile at -O3 since r14-4077-g86451305d8b

[ewlu at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119114

            Bug ID: 119114
           Summary: [14/15 regression] RISC-V: miscompile at -O3 since
                    r14-4077-g86451305d8b
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ewlu at rivosinc dot com
  Target Milestone: ---

testcase:

_Bool a;
short b[18];
long long al;
_Bool e;
char f = 010;
short t[18];
unsigned short w[8][18][18][18];

void c(_Bool e, char f, short t[], unsigned short w[][18][18][18]) {
  for (int ae = 1; ae < f + 5; ae += 2) {
    a -= (_Bool)(t[ae - 1] & t[ae + 3]);
    for (short af = 0; af < 18; af += 2)
      for (_Bool ah = 0; ah < (w[e][1][af][0] > 0); ah = 5)
        b[af] |= 9;
  }
}

int main() {
  for (int ad = 0; ad < 18; ad++)
    t[ad] = 3;
  c(e, f, t, w);
  al = a;
  __builtin_printf("%llu\n", al);
}

> /scratch/ewlu/daily-upstream-build/build-gcv/bin/riscv64-unknown-linux-gnu-gcc
>  -march=rv64gcv -flto -O3 -mrvv-vector-bits=zvl red.c -o user-config.out
> QEMU_CPU=rv64,vlen=128,rvv_ta_all_1s=true,rvv_ma_all_1s=true,v=true,vext_spec=v1.0,zve32f=true,zve64f=true
>  /scratch/ewlu/daily-upstream-build/build-gcv/bin/qemu-riscv64 
> user-config.out 1
1

> /scratch/ewlu/daily-upstream-build/build-gcv/bin/riscv64-unknown-linux-gnu-gcc
>  -march=rv64gcv -flto -O2 -mrvv-vector-bits=zvl red.c -o user-config.out
> QEMU_CPU=rv64,vlen=128,rvv_ta_all_1s=true,rvv_ma_all_1s=true,v=true,vext_spec=v1.0,zve32f=true,zve64f=true
>  /scratch/ewlu/daily-upstream-build/build-gcv/bin/qemu-riscv64 
> user-config.out 1
0

x86 outputs 0.

bisected to r14-4077-g86451305d8b as the first bad commit

found via fuzzer