https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122769
--- Comment #7 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
Some more trials and tribulations
riscv_emit_int_compare
if ((*code == GE)
&& (REG_P (*op0) || SUBREG_P (*op0))
&& *op1 == const0_rtx)
{
emit_insn (gen_slt_3 (LT, GET_MODE (*op0), GET_MODE (*op0), *op0, *op0,
*op1));
*code = EQ;
return;
}
Which requires relaxing the mode in slt pattern (below is just a hack as we
don't need two modes now, but this allows existing callers of gen_slt_3 to
remian unchanged.
-(define_insn "@slt<u>_<X:mode><GPR:mode>3"
+(define_insn "@slt<u>_<GPR:mode><GPR:mode>3"
[(set (match_operand:GPR 0 "register_operand" "= r")
- (any_lt:GPR (match_operand:X 1 "register_operand" " r")
- (match_operand:X 2 "arith_operand" " rI")))]
+ (any_lt:GPR (match_operand:GPR 1 "register_operand" " r")
+ (match_operand:GPR 2 "arith_operand" " rI")))]
This in turn requires the cbranch operands to be relaxed as well.
(define_insn "*branch<mode>"
[(set (pc)
(if_then_else
(match_operator 1 "ordered_comparison_operator"
- [(match_operand:X 2 "register_operand" "r")
- (match_operand:X 3 "reg_or_0_operand" "rJ")])
+ [(match_operand:GPR 2 "register_operand" "r")
+ (match_operand:GPR 3 "reg_or_0_operand" "rJ")])
Per discussions on IRC, the RTX_COMPARE patterns need not be X (64-bit only for
rv64gc), so this approach might not be totally absurd, however there must be
easier ways such as using a temp DI mode reg before calling the slt pattern.
