https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122769
--- Comment #14 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
Just as a proof of concept and for completeness some update on approach #1:
i.e. Expand time tweaking if_then_else GE 0 to if_then_else EQ 0 (with an
additional SLT)
The patch below fixes the orig reported test.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
@@ -5308,6 +5308,25 @@ riscv_emit_int_compare (enum rtx_code *code, rtx *op0,
rtx *op1,
*op0 = force_reg (word_mode, *op0);
if (*op1 != const0_rtx)
*op1 = force_reg (word_mode, *op1);
+
+ /* ifcvt/czero has better outcomes with EQ operator, so convert
+ if (a >= 0)
+ to
+ slti x, a, 0
+ if (x == 0)
+ slt patern expects input operands to be "X", thus needs to happen after
+ riscv_extend_comparands() which extends ops to DImode if rv64. */
+
+ if (*code == GE
+ && (REG_P (*op0))
+ && *op1 == const0_rtx)
+ {
+ rtx tmp = gen_reg_rtx (GET_MODE (*op0));
+ emit_insn (gen_slt_3 (LT, GET_MODE (*op0), GET_MODE (*op0), tmp, *op0,
*op1));
+ *code = EQ;
+ *op0 = tmp;
+ return;
+ }
It causes 8 additional testsuite failures, but those tests were deliberately
trying to inhibit CZERO for sign bit which runs counter to the orig ask here.
2025-08-22 ebbeaf490c56 [PR rtl-optimization/120553] Improve selecting between
constants based on sign bit test
2025-06-05 1d90f8c7933e [RISC-V] Improve sequences to generate -1, 1 in some
cases.
