https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121451
--- Comment #5 from Robin Dapp <rdapp at gcc dot gnu.org> --- (In reply to Zhongyao Chen from comment #4) > Had a quick look. > > Even if the uarch optimizes zero-stride loads as described in the RVV spec, > I wouldn't expect > > vlse64.v v3, 0(a1), zero > vfmacc.vv v1, v3, v2 > > better then > > fld fa5, 0(a4) > vfmacc.vf v1, fa5, v2 "Unfortunately" there are uarchs where the former sequence is better :) If there weren't, we could get rid of quite a bit of complexity.
