https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127768
Bug ID: 127768
Summary: Inefficient spilling/reloading of paradoxical subregs
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Keywords: missed-optimization, ra
Severity: normal
Priority: P3
Component: middle-end
Assignee: unassigned at gcc dot gnu.org
Reporter: rguenth at gcc dot gnu.org
CC: uros at gcc dot gnu.org, vmakarov at gcc dot gnu.org
Target Milestone: ---
Target: x86_64-*-*
The testcase from PR127606 shows
Before LRA we have:
(insn 219 218 220 3 (parallel [
(set (reg:SI 146 [ _47 ])
(xor:SI (reg:SI 343 [ df_91 ])
(subreg:SI (reg/v:QI 160 [ dl ]) 0)))
(clobber (reg:CC 17 flags))
]) "pr127606.c":180:13 860 {*xorsi_1}
(expr_list:REG_DEAD (reg:SI 343 [ df_91 ])
(expr_list:REG_UNUSED (reg:CC 17 flags)
(nil))))
Which LRA transforms to:
(insn 380 381 365 3 (set (mem/c:QI (plus:DI (reg/f:DI 7 sp)
(const_int 4 [0x4])) [11 %sfp+-52 S1 A32])
(reg/v:QI 4 si [orig:160 dl ] [160])) "pr127606.c":180:13 102
{*movqi_internal}
(nil))
(insn 365 380 219 3 (set (reg:SI 2 cx [410])
(mem/c:SI (plus:DI (reg/f:DI 7 sp)
(const_int 4 [0x4])) [11 %sfp+-52 S4 A32])) "pr127606.c":180:13
100 {*movsi_internal}
(nil))
(insn 219 365 220 3 (parallel [
(set (reg:SI 1 dx [orig:146 _47 ] [146])
(xor:SI (reg:SI 1 dx [orig:343 df_91 ] [343])
(reg:SI 2 cx [410])))
(clobber (reg:CC 17 flags))
]) "pr127606.c":180:13 860 {*xorsi_1}
(nil))
Please note spill in QImode and fill in SImode.
This is bad because a QImode store will not forward to a SImode load. One
fix for this would be to do a QImode load-extend (just loading QImode
will cause partial register stalls), but then this will still defeat
recent CPU uarchs capability to promote stack slots in their register
renaming phase. So spilling paradoxical subregs (< word_mode?) in their
full mode is likely most optimal.
Maybe targets want control of this as well (we do seem to allocate a full
SImode stack slot). I don't know how much control a target already has
for spill/reload instruction selection.
