[Bug rtl-optimization/128063] New: `op0 != 0 ? op0 & op1 : 0` can be optimized to just `op0 & op1` in RTL

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128063

            Bug ID: 128063
           Summary: `op0 != 0 ? op0 & op1 : 0` can be optimized to just
                    `op0 & op1` in RTL
           Product: gcc
           Version: 17.0
            Status: UNCONFIRMED
          Keywords: easyhack, missed-optimization
          Severity: normal
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pinskia at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64 x86_64

Take the following 2 functions:
```
int f(int a, int b, int c)
{
  if (a == 0)
    return 0;
  return a & (b >> c);
}

int f1(int a, int b)
{
  if (a == 0)
    return 0;
  return a & __builtin_ctz(b);
}

```

These 2 should not contain a cmov/csel.

What needs to be optimized is (for example on aarch64):
```
Trying 42, 43 -> 21:
   42: r109:SI=r106:SI&r103:SI
      REG_DEAD r106:SI
   43: cc:CC=cmp(r103:SI,0)
      REG_DEAD r103:SI
   21: x0:SI={(cc:CC!=0)?r109:SI:0}
      REG_DEAD cc:CC
      REG_DEAD r109:SI
Failed to match this instruction:
(set (reg/i:SI 0 x0)
    (if_then_else:SI (ne (reg/v:SI 103 [ aD.4455 ])
            (const_int 0 [0]))
        (and:SI (reg:SI 106 [ _1 ])
            (reg/v:SI 103 [ aD.4455 ]))
        (const_int 0 [0])))
```

This should be simplified into just:
```
(set (reg/i:SI 0 x0)
     (and:SI (reg:SI 106 [ _1 ])
             (reg/v:SI 103 [ aD.4455 ])))
```

This should be simple to implement in simplify-rtx.cc even.