https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128432
Bug ID: 128432
Summary: Vectorization to do float_truncate fails if there are
2 floating point formats that are the same size
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
I have implemented 16-bit floating point support in the PowerPC that I want to
check in. I have implemented support for both the IEEE 754 16-bit floating
point (_Float16) and the Google 16-bit brain floating point (__bf16).
Unfortunately the named insn "vec_pack_trunc_<mode>" assumes there is only one
floating format that is 1/2 the size of <mode>.
This means I can only have one 16-bit floating point format that is
automatically vectorized. At the moment, I have selected the Goggle brain
format as the format that gets vectorized. I.e. vec_pack_trunc_v4sf does
vectorized conversion from a pair of V4SF operands to convert to a V8BF
operand.
I would propose that in addition to vec_pack_trunc_<mode> that we have an
alternate form as vec_pack_trunc_<from-mode><to-mode>. I.e. in the PowerPC, I
could define both vec_pack_trunc_v4sfv8bf and vec_pack_trunc_v4sfv8hf. At the
moment I have an '_' between v4sf and v8bf or v8hf, but I can easily change
that.
For example with my current patches, the following code (note, I have turned
off unrolling to make it clearer):
add_vector_vector_bf16_unroll0 (__bf16 *__restrict__ p,
__bf16 *__restrict__ q,
__bf16 *__restrict__ r)
{
unsigned long i;
#pragma GCC unroll 0
for (i = 0; i < SIZE; i++)
p[i] = q[i] + r[i];
}
void
add_vector_vector_float16_unroll0 (_Float16 *__restrict__ p,
_Float16 *__restrict__ q,
_Float16 *__restrict__ r)
{
unsigned long i;
#pragma GCC unroll 0
for (i = 0; i < SIZE; i++)
p[i] = q[i] + r[i];
}
Generates:
add_vector_vector_bf16_unroll0:
li 9,128
li 2,0
mtctr 9
.p2align 4,,15
.L13:
lxvx 0,5,2
lxvx 12,4,2
plxv 43,.LC0@pcrel
xxlor 39,0,0
xxlor 40,12,12
vmrglh 1,7,7
vmrglh 12,8,8
vmrghh 0,7,7
vmrghh 13,8,8
xvcvbf16spn 33,33
xvcvbf16spn 8,44
xvcvbf16spn 32,32
xvcvbf16spn 10,45
xvaddsp 33,33,8
xvaddsp 32,32,10
xvcvspbf16 33,33
xvcvspbf16 32,32
vperm 0,0,1,11
stxvx 32,3,2
addi 2,2,16
bdnz .L13
blr
add_vector_vector_float16_unroll0:
li 9,1024
li 2,0
mtctr 9
.p2align 4,,15
.L16:
lxsihzx 0,4,2
lxsihzx 12,5,2
xscvhpdp 0,0
xscvhpdp 12,12
fadds 0,0,12
xscvdphp 0,0
stxsihx 0,3,2
addi 2,2,2
bdnz .L16
blr