https://gcc.gnu.org/g:3d0f38b394e6c5f4bb93ce2047dd985ea7e081af
commit 3d0f38b394e6c5f4bb93ce2047dd985ea7e081af
Author: Vineet Gupta <vine...@rivosinc.com>
Date: Tue Mar 1 03:45:19 2022 -0800
RISC-V: miscll comment fixes [NFC]
gcc/ChangeLog:
* config/riscv/riscv.cc: Comment updates.
* config/riscv/riscv.h: Ditto.
Signed-off-by: Vineet Gupta <vine...@rivosinc.com>
(cherry picked from commit 467ca4a195e26dba77e7f62cc1a3d45a4e541c72)
Diff:
---
gcc/config/riscv/riscv.cc | 6 ++++--
gcc/config/riscv/riscv.h | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8ed9df8126a6..44945d47fd64 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1258,7 +1258,9 @@ riscv_legitimate_constant_p (machine_mode mode
ATTRIBUTE_UNUSED, rtx x)
return riscv_const_insns (x) > 0;
}
-/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
+/* Implement TARGET_CANNOT_FORCE_CONST_MEM.
+ Return true if X cannot (or should not) be spilled to the
+ constant pool. */
static bool
riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
@@ -8624,7 +8626,7 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode
mode2)
&& GET_MODE_CLASS (mode2) == MODE_FLOAT));
}
-/* Implement CLASS_MAX_NREGS. */
+/* Implement TARGET_CLASS_MAX_NREGS. */
static unsigned char
riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 7797e67317a6..58d0b09bf7d9 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -315,7 +315,7 @@ ASM_MISA_SPEC
- FRAME_POINTER_REGNUM
- 1 vl register
- 1 vtype register
- - 30 unused registers for future expansion
+ - 28 unused registers for future expansion
- 32 vector registers */
#define FIRST_PSEUDO_REGISTER 128
