https://gcc.gnu.org/g:29da986382e18e274da118fcdffda23c4beea8dc
commit 29da986382e18e274da118fcdffda23c4beea8dc Author: Michael Meissner <[email protected]> Date: Fri Feb 13 03:02:51 2026 -0500 Revert changes Diff: --- gcc/config/rs6000/constraints.md | 3 - gcc/config/rs6000/predicates.md | 38 ------- gcc/config/rs6000/rs6000-c.cc | 4 - gcc/config/rs6000/rs6000.cc | 228 +++++++-------------------------------- gcc/config/rs6000/rs6000.h | 38 +------ gcc/config/rs6000/rs6000.opt | 4 - gcc/doc/md.texi | 5 - 7 files changed, 46 insertions(+), 274 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 0d1cde5bd4de..d0ed47faab84 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -107,9 +107,6 @@ (match_test "TARGET_P8_VECTOR") (match_operand 0 "s5bit_cint_operand"))) -(define_register_constraint "wD" "rs6000_constraints[RS6000_CONSTRAINT_wD]" - "Accumulator register.") - (define_constraint "wE" "@internal Vector constant that can be loaded with the XXSPLTIB instruction." (match_test "xxspltib_constant_nosplit (op, mode)")) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 5de81d54507b..54dbc8bcc952 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -186,44 +186,6 @@ return VLOGICAL_REGNO_P (REGNO (op)); }) -;; Return 1 if op is a dense math register -(define_predicate "dense_math_operand" - (match_operand 0 "register_operand") -{ - if (!REG_P (op)) - return 0; - - if (!HARD_REGISTER_P (op)) - return 1; - - return DM_REGNO_P (REGNO (op)); -}) - -;; Return 1 if op is an accumulator. -;; -;; On power10 and power11 systems, the accumulators overlap with the -;; FPRs and the register must be divisible by 4. -;; -;; On systems with dense math registers, the accumulators are separate -;; registers and do not overlap with the FPR registers. -(define_predicate "accumulator_operand" - (match_operand 0 "register_operand") -{ - if (SUBREG_P (op)) - op = SUBREG_REG (op); - - if (!REG_P (op)) - return 0; - - if (!HARD_REGISTER_P (op)) - return 1; - - int r = REGNO (op); - return (TARGET_DENSE_MATH - ? DM_REGNO_P (r) - : FP_REGNO_P (r) && (r & 3) == 0); -}) - ;; Return 1 if op is the carry register. (define_predicate "ca_operand" (match_operand 0 "register_operand") diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index a7eb951b014d..eb6a881aa9bd 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -590,10 +590,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) /* Tell the user if we support the MMA instructions. */ if ((flags & OPTION_MASK_MMA) != 0) rs6000_define_or_undefine_macro (define_p, "__MMA__"); - /* Tell the user if we support the dense math registers for use with MMA and - cryptography. */ - if ((flags & OPTION_MASK_DENSE_MATH) != 0) - rs6000_define_or_undefine_macro (define_p, "__DENSE_MATH__"); /* Whether pc-relative code is being generated. */ if ((flags & OPTION_MASK_PCREL) != 0) rs6000_define_or_undefine_macro (define_p, "__PCREL__"); diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 2587c00301f7..3886f1d46c46 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -292,8 +292,7 @@ enum rs6000_reg_type { ALTIVEC_REG_TYPE, FPR_REG_TYPE, SPR_REG_TYPE, - CR_REG_TYPE, - DM_REG_TYPE + CR_REG_TYPE }; /* Map register class to register type. */ @@ -307,24 +306,22 @@ static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES]; /* Register classes we care about in secondary reload or go if legitimate - address. We only need to worry about GPR, FPR, Altivec, and dense math - registers here, along an ANY field that is the OR of the 4 register - classes. */ + address. We only need to worry about GPR, FPR, and Altivec registers here, + along an ANY field that is the OR of the 3 register classes. */ enum rs6000_reload_reg_type { RELOAD_REG_GPR, /* General purpose registers. */ RELOAD_REG_FPR, /* Traditional floating point regs. */ RELOAD_REG_VMX, /* Altivec (VMX) registers. */ - RELOAD_REG_DMR, /* Dense math registers. */ - RELOAD_REG_ANY, /* OR of GPR/FPR/VMX/DMR masks. */ + RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */ N_RELOAD_REG }; -/* For setting up register classes, loop through the 4 register classes mapping +/* For setting up register classes, loop through the 3 register classes mapping into real registers, and skip the ANY class, which is just an OR of the bits. */ #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR -#define LAST_RELOAD_REG_CLASS RELOAD_REG_DMR +#define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX /* Map reload register type to a register in the register class. */ struct reload_reg_map_type { @@ -336,7 +333,6 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = { { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */ { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */ { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */ - { "Dmr", FIRST_DM_REGNO }, /* RELOAD_REG_DMR. */ { "Any", -1 }, /* RELOAD_REG_ANY. */ }; @@ -1230,8 +1226,6 @@ char rs6000_reg_names[][8] = "0", "1", "2", "3", "4", "5", "6", "7", /* vrsave vscr sfp */ "vrsave", "vscr", "sfp", - /* dense math registers. */ - "0", "1", "2", "3", "4", "5", "6", "7", }; #ifdef TARGET_REGNAMES @@ -1258,8 +1252,6 @@ static const char alt_reg_names[][8] = "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", /* vrsave vscr sfp */ "vrsave", "vscr", "sfp", - /* dense math registers. */ - "%dmr0", "%dmr1", "%dmr2", "%dmr3", "%dmr4", "%dmr5", "%dmr6", "%dmr7", }; #endif @@ -1850,9 +1842,6 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode) else if (ALTIVEC_REGNO_P (regno)) reg_size = UNITS_PER_ALTIVEC_WORD; - else if (DM_REGNO_P (regno)) - reg_size = UNITS_PER_DM_WORD; - else reg_size = UNITS_PER_WORD; @@ -1874,32 +1863,9 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) if (mode == OOmode) return (TARGET_MMA && VSX_REGNO_P (regno) && (regno & 1) == 0); - /* On ISA 3.1 (power10), MMA accumulator modes need FPR registers divisible - by 4. - - If dense math registers are enabled, we can allow all VSX registers plus - the dense math registers. VSX registers are used to load and store the - registers as the accumulator registers do not have load and store - instructions. Because we just use the VSX registers for load/store - operations, we just need to make sure load vector pair and store vector - pair instructions can be used. */ + /* MMA accumulator modes need FPR registers divisible by 4. */ if (mode == XOmode) - { - if (!TARGET_DENSE_MATH) - return (FP_REGNO_P (regno) && (regno & 3) == 0); - - else if (DM_REGNO_P (regno)) - return 1; - - else - return (VSX_REGNO_P (regno) - && VSX_REGNO_P (last_regno) - && (regno & 1) == 0); - } - - /* No other types other than XOmode can go in dense math registers. */ - if (DM_REGNO_P (regno)) - return 0; + return (TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0); /* PTImode can only go in GPRs. Quad word memory operations require even/odd register combinations, and use PTImode where we need to deal with quad @@ -2342,7 +2308,6 @@ rs6000_debug_reg_global (void) rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO, "vs"); - rs6000_debug_reg_print (FIRST_DM_REGNO, LAST_DM_REGNO, "dense_math"); rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr"); rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr"); rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr"); @@ -2363,7 +2328,6 @@ rs6000_debug_reg_global (void) "wr reg_class = %s\n" "wx reg_class = %s\n" "wA reg_class = %s\n" - "wD reg_class = %s\n" "\n", reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]], @@ -2371,8 +2335,7 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wD]]); + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]); nl = "\n"; for (m = 0; m < NUM_MACHINE_MODES; ++m) @@ -2669,21 +2632,6 @@ rs6000_setup_reg_addr_masks (void) addr_mask = 0; reg = reload_reg_map[rc].reg; - /* Special case dense math registers. */ - if (rc == RELOAD_REG_DMR) - { - if (TARGET_DENSE_MATH && m2 == XOmode) - { - addr_mask = RELOAD_REG_VALID; - reg_addr[m].addr_mask[rc] = addr_mask; - any_addr_mask |= addr_mask; - } - else - reg_addr[m].addr_mask[rc] = 0; - - continue; - } - /* Can mode values go in the GPR/FPR/Altivec registers? */ if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg]) { @@ -2834,9 +2782,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) for (r = CR1_REGNO; r <= CR7_REGNO; ++r) rs6000_regno_regclass[r] = CR_REGS; - for (r = FIRST_DM_REGNO; r <= LAST_DM_REGNO; ++r) - rs6000_regno_regclass[r] = DM_REGS; - rs6000_regno_regclass[LR_REGNO] = LINK_REGS; rs6000_regno_regclass[CTR_REGNO] = CTR_REGS; rs6000_regno_regclass[CA_REGNO] = NO_REGS; @@ -2861,7 +2806,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE; reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE; reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE; - reg_class_to_reg_type[(int)DM_REGS] = DM_REG_TYPE; if (TARGET_VSX) { @@ -3048,12 +2992,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_DIRECT_MOVE_128) rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS; - /* Support for the accumulator registers, either FPR registers (aka original - mma) or dense math registers. */ - if (TARGET_MMA) - rs6000_constraints[RS6000_CONSTRAINT_wD] - = TARGET_DENSE_MATH ? DM_REGS : FLOAT_REGS; - /* Set up the reload helper and direct move functions. */ if (TARGET_VSX || TARGET_ALTIVEC) { @@ -4467,15 +4405,6 @@ rs6000_option_override_internal (bool global_init_p) if (!TARGET_PCREL && TARGET_PCREL_OPT) rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; - /* Turn off dense math register support on non-future systems. */ - if (TARGET_DENSE_MATH && !TARGET_FUTURE) - { - if ((rs6000_isa_flags_explicit & OPTION_MASK_DENSE_MATH) != 0) - error ("%qs requires %qs", "-mdense-math", "-mcpu=future"); - - rs6000_isa_flags &= ~OPTION_MASK_DENSE_MATH; - } - if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags); @@ -12422,11 +12351,6 @@ rs6000_secondary_reload_memory (rtx addr, addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & ~RELOAD_REG_AND_M16); - /* Dense math registers use VSX registers for memory operations, and need to - generate some extra instructions. */ - else if (rclass == DM_REGS) - return 2; - /* If the register allocator hasn't made up its mind yet on the register class to use, settle on defaults to use. */ else if (rclass == NO_REGS) @@ -12755,13 +12679,6 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type, || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE))) return true; - /* We can transfer between VSX registers and dense math registers without - needing extra registers. */ - if (TARGET_DENSE_MATH && mode == XOmode - && ((to_type == DM_REG_TYPE && from_type == VSX_REG_TYPE) - || (to_type == VSX_REG_TYPE && from_type == DM_REG_TYPE))) - return true; - return false; } @@ -13456,10 +13373,6 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) machine_mode mode = GET_MODE (x); bool is_constant = CONSTANT_P (x); - /* Dense math registers can't be loaded or stored. */ - if (rclass == DM_REGS) - return NO_REGS; - /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred reload class for it. */ if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS) @@ -13556,7 +13469,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) return VSX_REGS; if (mode == XOmode) - return TARGET_DENSE_MATH ? VSX_REGS : FLOAT_REGS; + return FLOAT_REGS; if (GET_MODE_CLASS (mode) == MODE_INT) return GENERAL_REGS; @@ -13681,11 +13594,6 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode, else regno = -1; - /* Dense math registers don't have loads or stores. We have to go through - the VSX registers to load XOmode (vector quad). */ - if (TARGET_DENSE_MATH && rclass == DM_REGS) - return VSX_REGS; - /* If we have VSX register moves, prefer moving scalar values between Altivec registers and GPR by going via an FPR (and then via memory) instead of reloading the secondary memory address for Altivec moves. */ @@ -14217,14 +14125,8 @@ print_operand (FILE *file, rtx x, int code) output_operand. */ case 'A': - /* Write the MMA accumulator number associated with VSX register X. On - dense math systems, only allow dense math accumulators, not - accumulators overlapping with the FPR registers. */ - if (!REG_P (x)) - output_operand_lossage ("invalid %%A value"); - else if (TARGET_DENSE_MATH && DM_REGNO_P (REGNO (x))) - fprintf (file, "%d", REGNO (x) - FIRST_DM_REGNO); - else if (!FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0) + /* Write the MMA accumulator number associated with VSX register X. */ + if (!REG_P (x) || !FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0) output_operand_lossage ("invalid %%A value"); else fprintf (file, "%d", (REGNO (x) - FIRST_FPR_REGNO) / 4); @@ -22844,31 +22746,6 @@ rs6000_debug_address_cost (rtx x, machine_mode mode, } -/* Subroutine to determine the move cost of dense math registers. If we are - moving to/from VSX_REGISTER registers, the cost is either 1 move (for - 512-bit accumulators) or 2 moves (for 1,024 dense math registers). If we are - moving to anything else like GPR registers, make the cost very high. */ - -static int -rs6000_dense_math_register_move_cost (machine_mode mode, reg_class_t rclass) -{ - const int reg_move_base = 2; - HARD_REG_SET vsx_set = (reg_class_contents[rclass] - & reg_class_contents[VSX_REGS]); - - if (TARGET_DENSE_MATH && !hard_reg_set_empty_p (vsx_set)) - { - /* __vector_quad (i.e. XOmode) is tranfered in 1 instruction. */ - if (mode == XOmode) - return reg_move_base; - - else - return reg_move_base * 2 * hard_regno_nregs (FIRST_DM_REGNO, mode); - } - - return 1000 * 2 * hard_regno_nregs (FIRST_DM_REGNO, mode); -} - /* A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2. */ @@ -22882,28 +22759,17 @@ rs6000_register_move_cost (machine_mode mode, if (TARGET_DEBUG_COST) dbg_cost_ctrl++; - HARD_REG_SET to_vsx, from_vsx; - to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS]; - from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS]; - - /* Special case dense math registers, that can only move to/from VSX registers. */ - if (from == DM_REGS && to == DM_REGS) - ret = 2 * hard_regno_nregs (FIRST_DM_REGNO, mode); - - else if (from == DM_REGS) - ret = rs6000_dense_math_register_move_cost (mode, to); - - else if (to == DM_REGS) - ret = rs6000_dense_math_register_move_cost (mode, from); - /* If we have VSX, we can easily move between FPR or Altivec registers, otherwise we can only easily move within classes. Do this first so we give best-case answers for union classes containing both gprs and vsx regs. */ - else if (!hard_reg_set_empty_p (to_vsx) - && !hard_reg_set_empty_p (from_vsx) - && (TARGET_VSX - || hard_reg_set_intersect_p (to_vsx, from_vsx))) + HARD_REG_SET to_vsx, from_vsx; + to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS]; + from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS]; + if (!hard_reg_set_empty_p (to_vsx) + && !hard_reg_set_empty_p (from_vsx) + && (TARGET_VSX + || hard_reg_set_intersect_p (to_vsx, from_vsx))) { int reg = FIRST_FPR_REGNO; if (TARGET_VSX @@ -22999,9 +22865,6 @@ rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass, ret = 4 * hard_regno_nregs (32, mode); else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS)) ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode); - else if (reg_classes_intersect_p (rclass, DM_REGS)) - ret = (rs6000_dense_math_register_move_cost (mode, VSX_REGS) - + rs6000_memory_move_cost (mode, VSX_REGS, false)); else ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS); @@ -24210,8 +24073,6 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes) if (TARGET_HARD_FLOAT) pressure_classes[n++] = FLOAT_REGS; } - if (TARGET_DENSE_MATH) - pressure_classes[n++] = DM_REGS; pressure_classes[n++] = CR_REGS; pressure_classes[n++] = SPECIAL_REGS; @@ -24376,10 +24237,6 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format) return 67; if (regno == 64) return 64; - /* XXX: This is a guess. The GCC register number for FIRST_DM_REGNO is 111, - but the frame pointer regnum uses that. */ - if (DM_REGNO_P (regno)) - return regno - FIRST_DM_REGNO + 112; gcc_unreachable (); } @@ -24601,7 +24458,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = false, true }, { "cmpb", OPTION_MASK_CMPB, false, true }, { "crypto", OPTION_MASK_CRYPTO, false, true }, - { "dense-math", OPTION_MASK_DENSE_MATH, false, true }, { "direct-move", 0, false, true }, { "dlmzb", OPTION_MASK_DLMZB, false, true }, { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX, @@ -27619,9 +27475,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) unsigned offset = 0; unsigned size = GET_MODE_SIZE (reg_mode); - /* If we are reading an accumulator register, we have to deprime it - before we can access it unless we have dense math registers. */ - if (TARGET_MMA && !TARGET_DENSE_MATH + /* If we are reading an accumulator register, we have to + deprime it before we can access it. */ + if (TARGET_MMA && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27653,9 +27509,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) emit_insn (gen_rtx_SET (dst2, src2)); } - /* If we are writing an accumulator register, we have to prime it - after we've written it unless we have dense math registers. */ - if (TARGET_MMA && !TARGET_DENSE_MATH + /* If we are writing an accumulator register, we have to + prime it after we've written it. */ + if (TARGET_MMA && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); @@ -27669,9 +27525,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) || XINT (src, 1) == UNSPECV_MMA_ASSEMBLE); gcc_assert (REG_P (dst)); if (GET_MODE (src) == XOmode) - gcc_assert ((TARGET_DENSE_MATH - ? VSX_REGNO_P (REGNO (dst)) - : FP_REGNO_P (REGNO (dst)))); + gcc_assert (FP_REGNO_P (REGNO (dst))); if (GET_MODE (src) == OOmode) gcc_assert (VSX_REGNO_P (REGNO (dst))); @@ -27724,9 +27578,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) emit_insn (gen_rtx_SET (dst_i, op)); } - /* We are writing an accumulator register, so we have to prime it - after we've written it unless we have dense math registers. */ - if (GET_MODE (src) == XOmode && !TARGET_DENSE_MATH) + /* We are writing an accumulator register, so we have to + prime it after we've written it. */ + if (GET_MODE (src) == XOmode) emit_insn (gen_mma_xxmtacc (dst, dst)); return; @@ -27737,9 +27591,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) { - /* If we are reading an accumulator register, we have to deprime it - before we can access it unless we have dense math registers. */ - if (TARGET_MMA && !TARGET_DENSE_MATH + /* If we are reading an accumulator register, we have to + deprime it before we can access it. */ + if (TARGET_MMA && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27765,9 +27619,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) i * reg_mode_size))); } - /* If we are writing an accumulator register, we have to prime it after - we've written it unless we have dense math registers. */ - if (TARGET_MMA && !TARGET_DENSE_MATH + /* If we are writing an accumulator register, we have to + prime it after we've written it. */ + if (TARGET_MMA && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); } @@ -27902,9 +27756,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true)); } - /* If we are reading an accumulator register, we have to deprime it - before we can access it unless we have dense math registers. */ - if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (src) + /* If we are reading an accumulator register, we have to + deprime it before we can access it. */ + if (TARGET_MMA && REG_P (src) && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27934,9 +27788,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) j * reg_mode_size))); } - /* If we are writing an accumulator register, we have to prime it after - we've written it unless we have dense math registers. */ - if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (dst) + /* If we are writing an accumulator register, we have to + prime it after we've written it. */ + if (TARGET_MMA && REG_P (dst) && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 5214a7c22cea..2d3016db5135 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -653,7 +653,6 @@ extern unsigned char rs6000_recip_bits[]; #define UNITS_PER_FP_WORD 8 #define UNITS_PER_ALTIVEC_WORD 16 #define UNITS_PER_VSX_WORD 16 -#define UNITS_PER_DM_WORD 128 /* Type used for ptrdiff_t, as a string used in a declaration. */ #define PTRDIFF_TYPE "int" @@ -767,7 +766,7 @@ enum data_align { align_abi, align_opt, align_both }; Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame pointer, which is eventually eliminated in favor of SP or FP. */ -#define FIRST_PSEUDO_REGISTER 119 +#define FIRST_PSEUDO_REGISTER 111 /* Use standard DWARF numbering for DWARF debugging information. */ #define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0) @@ -804,9 +803,7 @@ enum data_align { align_abi, align_opt, align_both }; /* cr0..cr7 */ \ 0, 0, 0, 0, 0, 0, 0, 0, \ /* vrsave vscr sfp */ \ - 1, 1, 1, \ - /* Dense math registers. */ \ - 0, 0, 0, 0, 0, 0, 0, 0 \ + 1, 1, 1 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that @@ -830,9 +827,7 @@ enum data_align { align_abi, align_opt, align_both }; /* cr0..cr7 */ \ 1, 1, 0, 0, 0, 1, 1, 1, \ /* vrsave vscr sfp */ \ - 0, 0, 0, \ - /* Dense math registers. */ \ - 0, 0, 0, 0, 0, 0, 0, 0 \ + 0, 0, 0 \ } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) @@ -869,7 +864,6 @@ enum data_align { align_abi, align_opt, align_both }; v2 (not saved; incoming vector arg reg; return value) v19 - v14 (not saved or used for anything) v31 - v20 (saved; order given to save least number) - dmr0 - dmr7 (not saved) vrsave, vscr (fixed) sfp (fixed) */ @@ -912,9 +906,6 @@ enum data_align { align_abi, align_opt, align_both }; 66, \ 83, 82, 81, 80, 79, 78, \ 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ - /* Dense math registers. */ \ - 111, 112, 113, 114, 115, 116, 117, 118, \ - /* Vrsave, vscr, sfp. */ \ 108, 109, \ 110 \ } @@ -941,9 +932,6 @@ enum data_align { align_abi, align_opt, align_both }; /* True if register is a VSX register. */ #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) -/* True if register is a Dense math register. */ -#define DM_REGNO_P(N) ((N) >= FIRST_DM_REGNO && (N) <= LAST_DM_REGNO) - /* Alternate name for any vector register supporting floating point, no matter which instruction set(s) are available. */ #define VFLOAT_REGNO_P(N) \ @@ -1081,7 +1069,6 @@ enum reg_class FLOAT_REGS, ALTIVEC_REGS, VSX_REGS, - DM_REGS, VRSAVE_REGS, VSCR_REGS, GEN_OR_FLOAT_REGS, @@ -1111,7 +1098,6 @@ enum reg_class "FLOAT_REGS", \ "ALTIVEC_REGS", \ "VSX_REGS", \ - "DM_REGS", \ "VRSAVE_REGS", \ "VSCR_REGS", \ "GEN_OR_FLOAT_REGS", \ @@ -1146,8 +1132,6 @@ enum reg_class { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ /* VSX_REGS. */ \ { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ - /* DM_REGS. */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x007f8000 }, \ /* VRSAVE_REGS. */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ /* VSCR_REGS. */ \ @@ -1175,7 +1159,7 @@ enum reg_class /* CA_REGS. */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \ /* ALL_REGS. */ \ - { 0xffffffff, 0xffffffff, 0xffffffff, 0x007fffff } \ + { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \ } /* The same information, inverted: @@ -1199,7 +1183,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ - RS6000_CONSTRAINT_wD, /* Accumulator regs if MMA/Dense Math. */ RS6000_CONSTRAINT_MAX }; @@ -2076,16 +2059,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ &rs6000_reg_names[108][0], /* vrsave */ \ &rs6000_reg_names[109][0], /* vscr */ \ \ - &rs6000_reg_names[110][0], /* sfp */ \ - \ - &rs6000_reg_names[111][0], /* dmr0 */ \ - &rs6000_reg_names[112][0], /* dmr1 */ \ - &rs6000_reg_names[113][0], /* dmr2 */ \ - &rs6000_reg_names[114][0], /* dmr3 */ \ - &rs6000_reg_names[115][0], /* dmr4 */ \ - &rs6000_reg_names[116][0], /* dmr5 */ \ - &rs6000_reg_names[117][0], /* dmr6 */ \ - &rs6000_reg_names[118][0], /* dmr7 */ \ + &rs6000_reg_names[110][0] /* sfp */ \ } /* Table of additional register names to use in user input. */ @@ -2139,8 +2113,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \ {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \ {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \ - {"dmr0", 111}, {"dmr1", 112}, {"dmr2", 113}, {"dmr3", 114}, \ - {"dmr4", 115}, {"dmr5", 116}, {"dmr6", 117}, {"dmr7", 118}, \ } /* This is how to output an element of a case-vector that is relative. */ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index f836d1982877..9f3519da77b2 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -639,10 +639,6 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. -mdense-math -Target Mask(DENSE_MATH) Var(rs6000_isa_flags) -Generate (do not generate) instructions that use dense math registers. - ; Documented parameters -param=rs6000-vect-unroll-limit= diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 2b7f90ce5370..edbdb1d50f1a 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3415,11 +3415,6 @@ Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}. @item wA Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}. -@item wD -Accumulator register if @option{-mma} is used; otherwise, -@code{NO_REGS}. For @option{-mcpu=power10} the accumulator registers -overlap with VSX vector registers 0..31. - @item wB Signed 5-bit constant integer that can be loaded into an Altivec register.
