https://gcc.gnu.org/g:0974a917a5e087b6d078b926c778c4f0d2f6b25b
commit 0974a917a5e087b6d078b926c778c4f0d2f6b25b Author: Michael Meissner <[email protected]> Date: Fri Feb 13 17:13:44 2026 -0500 Revert changes Diff: --- gcc/config/rs6000/mma.md | 283 +++----------------------- gcc/config/rs6000/rs6000-builtin.cc | 22 +- gcc/config/rs6000/rs6000-call.cc | 10 +- gcc/config/rs6000/rs6000-cpus.def | 2 - gcc/config/rs6000/rs6000-modes.def | 4 - gcc/config/rs6000/rs6000.cc | 112 +++------- gcc/config/rs6000/rs6000.h | 6 +- gcc/testsuite/gcc.target/powerpc/dm-1024bit.c | 63 ------ gcc/testsuite/gcc.target/powerpc/mma-dm-1.c | 67 ------ gcc/testsuite/gcc.target/powerpc/mma-dm-2.c | 67 ------ gcc/testsuite/lib/target-supports.exp | 35 ---- 11 files changed, 62 insertions(+), 609 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 06f88d6b5263..1813adbecd31 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -90,12 +90,6 @@ UNSPEC_MMA_XVI8GER4SPP UNSPEC_MMA_XXMFACC UNSPEC_MMA_XXMTACC - UNSPEC_MMA_DMSETDMRZ - UNSPEC_DM_INSERT512_UPPER - UNSPEC_DM_INSERT512_LOWER - UNSPEC_DM_EXTRACT512 - UNSPEC_DM_RELOAD_FROM_MEMORY - UNSPEC_DM_RELOAD_TO_MEMORY ]) (define_c_enum "unspecv" @@ -493,68 +487,31 @@ DONE; }) -;; If dense math registers are not available, MMA instructions that do -;; not use their accumulators that overlap with FPR registers as an -;; input, still must not allow their vector operands to overlap the -;; registers used by the accumulator. We enforce this by marking the -;; output as early clobber. The prime and de-prime instructions are -;; not needed on systems with dense math registers. +;; MMA instructions that do not use their accumulators as an input, still +;; must not allow their vector operands to overlap the registers used by +;; the accumulator. We enforce this by marking the output as early clobber. (define_insn "mma_<acc>" [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")] MMA_ACC))] - "TARGET_MMA && !TARGET_DENSE_MATH" + "TARGET_MMA" "<acc> %A0" [(set_attr "type" "mma")]) ;; We can't have integer constants in XOmode so we wrap this in an -;; UNSPEC_VOLATILE. If we have dense math registers, we can just use a normal -;; UNSPEC instead of UNSPEC_VOLATILE. - -(define_expand "mma_xxsetaccz" - [(set (match_operand:XO 0 "accumulator_operand") - (unspec_volatile:XO [(const_int 0)] - UNSPECV_MMA_XXSETACCZ))] - "TARGET_MMA" -{ - if (TARGET_DENSE_MATH) - { - emit_insn (gen_mma_xxsetaccz_dm (operands[0])); - DONE; - } -}) +;; UNSPEC_VOLATILE. -;; Clear accumulator without dense math registers -(define_insn "*mma_xxsetaccz_nodm" +(define_insn "mma_xxsetaccz" [(set (match_operand:XO 0 "fpr_reg_operand" "=d") (unspec_volatile:XO [(const_int 0)] UNSPECV_MMA_XXSETACCZ))] - "TARGET_MMA && !TARGET_DENSE_MATH" + "TARGET_MMA" "xxsetaccz %A0" [(set_attr "type" "mma")]) -;; Clear accumulator when dense math registers are available. -(define_insn "mma_xxsetaccz_dm" - [(set (match_operand:XO 0 "accumulator_operand" "=wD") - (unspec [(const_int 0)] - UNSPEC_MMA_DMSETDMRZ))] - "TARGET_DENSE_MATH" - "dmsetdmrz %A0" - [(set_attr "type" "mma")]) - - -;; MMA operations below. If dense math registers are available, these -;; operations will use the 8 accumultors which are separate registers. -;; If dense math registers are not available, these operations will use -;; accumulators that are overlaid on top of the FPR registers. - -;; Instructions: -;; xvi4ger8 xvi8ger4 xvi16ger2 xvi16ger2s xvf16ger2 -;; xvbf16ger2 xvf32ger - (define_insn "mma_<vv>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")] MMA_VV))] @@ -562,15 +519,9 @@ "<vv> %A0,%x1,%x2" [(set_attr "type" "mma")]) -;; Instructions: -;; xvi4ger8pp xvi8ger4pp xvi8ger4spp xvi16ger2pp xvi16ger2spp -;; xvf16ger2pp xvf16ger2pn xvf16ger2np xvf16ger2nn xvbf16ger2pp -;; xvbf16ger2pn xvbf16ger2np xvbf16ger2nn xvf32gerpp xvf32gerpn -;; xvf32gernp xvf32gernn - (define_insn "mma_<avv>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")] MMA_AVV))] @@ -578,10 +529,8 @@ "<avv> %A0,%x2,%x3" [(set_attr "type" "mma")]) -;; Instruction: xvf64ger - (define_insn "mma_<pv>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")] MMA_PV))] @@ -589,11 +538,9 @@ "<pv> %A0,%x1,%x2" [(set_attr "type" "mma")]) -;; Instructions: xvf64gerpp xvf64gerpn xvf64gernp xvf64gernn - (define_insn "mma_<apv>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") (match_operand:OO 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")] MMA_APV))] @@ -601,10 +548,8 @@ "<apv> %A0,%x2,%x3" [(set_attr "type" "mma")]) -;; Instruction: pmxvi4ger8 - (define_insn "mma_<vvi4i4i8>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:SI 3 "const_0_to_15_operand" "n,n") @@ -616,11 +561,9 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instruction: pmxvi4ger8pp - (define_insn "mma_<avvi4i4i8>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") (match_operand:SI 4 "const_0_to_15_operand" "n,n") @@ -632,11 +575,8 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instructions: -;; pmxvi16ger2 pmxvi16ger2s pmxvf16ger2 pmxvbf16ger2 - (define_insn "mma_<vvi4i4i2>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:SI 3 "const_0_to_15_operand" "n,n") @@ -648,14 +588,9 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instructions: -;; pmxvi16ger2pp pmxvi16ger2spp pmxvf16ger2pp pmxvf16ger2pn -;; pmxvf16ger2np pmxvf16ger2nn pmxvbf16ger2pp pmxvbf16ger2pn -;; pmxvbf16ger2np pmxvbf16ger2nn - (define_insn "mma_<avvi4i4i2>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") (match_operand:SI 4 "const_0_to_15_operand" "n,n") @@ -667,10 +602,8 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instruction: pmxvf32ger - (define_insn "mma_<vvi4i4>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:SI 3 "const_0_to_15_operand" "n,n") @@ -681,11 +614,9 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instructions: pmxvf32gerpp pmxvf32gerpn pmxvf32gernp pmxvf32gernn - (define_insn "mma_<avvi4i4>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") (match_operand:SI 4 "const_0_to_15_operand" "n,n") @@ -696,10 +627,8 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instruction: pmxvf64ger - (define_insn "mma_<pvi4i2>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:SI 3 "const_0_to_15_operand" "n,n") @@ -710,11 +639,9 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instructions: pmxvf64gerpp pmxvf64gerpn pmxvf64gernp pmxvf64gernn - (define_insn "mma_<apvi4i2>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") (match_operand:OO 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") (match_operand:SI 4 "const_0_to_15_operand" "n,n") @@ -725,10 +652,8 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instruction: pmxvi8ger4 - (define_insn "mma_<vvi4i4i4>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:SI 3 "const_0_to_15_operand" "n,n") @@ -740,11 +665,9 @@ [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) -;; Instructions: pmxvi8ger4pp pmxvi8ger4spp - (define_insn "mma_<avvi4i4i4>" - [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD") - (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0") + [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d") + (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0") (match_operand:V16QI 2 "vsx_register_operand" "v,?wa") (match_operand:V16QI 3 "vsx_register_operand" "v,?wa") (match_operand:SI 4 "const_0_to_15_operand" "n,n") @@ -755,153 +678,3 @@ "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") (set_attr "prefixed" "yes")]) - -;; TDOmode (__dmf keyword for 1,024 bit registers). -(define_expand "movtdo" - [(set (match_operand:TDO 0 "nonimmediate_operand") - (match_operand:TDO 1 "input_operand"))] - "TARGET_DENSE_MATH" -{ - rs6000_emit_move (operands[0], operands[1], TDOmode); - DONE; -}) - -(define_insn_and_split "*movtdo" - [(set (match_operand:TDO 0 "nonimmediate_operand" "=wa,m,wa,wD,wD,wa") - (match_operand:TDO 1 "input_operand" "m,wa,wa,wa,wD,wD"))] - "TARGET_DENSE_MATH - && (gpc_reg_operand (operands[0], TDOmode) - || gpc_reg_operand (operands[1], TDOmode))" - "@ - # - # - # - # - dmmr %0,%1 - #" - "&& reload_completed - && (!dense_math_operand (operands[0], TDOmode) - || !dense_math_operand (operands[1], TDOmode))" - [(const_int 0)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - - if (REG_P (op0) && REG_P (op1)) - { - int regno0 = REGNO (op0); - int regno1 = REGNO (op1); - - if (DM_REGNO_P (regno0) && VSX_REGNO_P (regno1)) - { - rtx op1_upper = gen_rtx_REG (XOmode, regno1); - rtx op1_lower = gen_rtx_REG (XOmode, regno1 + 4); - emit_insn (gen_movtdo_insert512_upper (op0, op1_upper)); - emit_insn (gen_movtdo_insert512_lower (op0, op0, op1_lower)); - DONE; - } - - else if (VSX_REGNO_P (regno0) && DM_REGNO_P (regno1)) - { - rtx op0_upper = gen_rtx_REG (XOmode, regno0); - rtx op0_lower = gen_rtx_REG (XOmode, regno0 + 4); - emit_insn (gen_movtdo_extract512 (op0_upper, op1, const0_rtx)); - emit_insn (gen_movtdo_extract512 (op0_lower, op1, const1_rtx)); - DONE; - } - - else - gcc_assert (VSX_REGNO_P (regno0) && VSX_REGNO_P (regno1)); - } - - rs6000_split_multireg_move (operands[0], operands[1]); - DONE; -} - [(set_attr "type" "vecload,vecstore,vecmove,vecmove,vecmove,vecmove") - (set_attr "length" "*,*,32,8,*,8") - (set_attr "max_prefixed_insns" "4,4,*,*,*,*")]) - -;; Move from VSX registers to dense math registers via two insert 512 bit -;; instructions. -(define_insn "movtdo_insert512_upper" - [(set (match_operand:TDO 0 "dense_math_operand" "=wD") - (unspec:TDO [(match_operand:XO 1 "vsx_register_operand" "wa")] - UNSPEC_DM_INSERT512_UPPER))] - "TARGET_DENSE_MATH" - "dmxxinstdmr512 %0,%1,%Y1,0" - [(set_attr "type" "mma")]) - -(define_insn "movtdo_insert512_lower" - [(set (match_operand:TDO 0 "dense_math_operand" "=wD") - (unspec:TDO [(match_operand:TDO 1 "dense_math_operand" "0") - (match_operand:XO 2 "vsx_register_operand" "wa")] - UNSPEC_DM_INSERT512_LOWER))] - "TARGET_DENSE_MATH" - "dmxxinstdmr512 %0,%2,%Y2,1" - [(set_attr "type" "mma")]) - -;; Move from dense math registers to VSX registers via two extract 512 bit -;; instructions. -(define_insn "movtdo_extract512" - [(set (match_operand:XO 0 "vsx_register_operand" "=wa") - (unspec:XO [(match_operand:TDO 1 "dense_math_operand" "wD") - (match_operand 2 "const_0_to_1_operand" "n")] - UNSPEC_DM_EXTRACT512))] - "TARGET_DENSE_MATH" - "dmxxextfdmr512 %0,%Y0,%1,%2" - [(set_attr "type" "mma")]) - -;; Reload dense math registers from memory. -(define_insn_and_split "reload_tdo_from_memory" - [(set (match_operand:TDO 0 "dense_math_operand" "=wD") - (unspec:TDO [(match_operand:TDO 1 "memory_operand" "m")] - UNSPEC_DM_RELOAD_FROM_MEMORY)) - (clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))] - "TARGET_DENSE_MATH" - "#" - "&& reload_completed" - [(const_int 0)] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - rtx tmp = operands[2]; - rtx mem_upper = adjust_address (src, XOmode, BYTES_BIG_ENDIAN ? 0 : 64); - rtx mem_lower = adjust_address (src, XOmode, BYTES_BIG_ENDIAN ? 64 : 0); - - emit_move_insn (tmp, mem_upper); - emit_insn (gen_movtdo_insert512_upper (dest, tmp)); - - emit_move_insn (tmp, mem_lower); - emit_insn (gen_movtdo_insert512_lower (dest, dest, tmp)); - DONE; -} - [(set_attr "length" "16") - (set_attr "max_prefixed_insns" "2") - (set_attr "type" "vecload")]) - -;; Reload dense math registers to memory -(define_insn_and_split "reload_tdo_to_memory" - [(set (match_operand:TDO 0 "memory_operand" "=m") - (unspec:TDO [(match_operand:TDO 1 "dense_math_operand" "wD")] - UNSPEC_DM_RELOAD_TO_MEMORY)) - (clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))] - "TARGET_DENSE_MATH" - "#" - "&& reload_completed" - [(const_int 0)] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - rtx tmp = operands[2]; - rtx mem_upper = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 0 : 64); - rtx mem_lower = adjust_address (dest, XOmode, BYTES_BIG_ENDIAN ? 64 : 0); - - emit_insn (gen_movtdo_extract512 (tmp, src, const0_rtx)); - emit_move_insn (mem_upper, tmp); - - emit_insn (gen_movtdo_extract512 (tmp, src, const1_rtx)); - emit_move_insn (mem_lower, tmp); - DONE; -} - [(set_attr "length" "16") - (set_attr "max_prefixed_insns" "2")]) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 88e5b3997f9e..45c88fe063b1 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -495,8 +495,6 @@ const char *rs6000_type_string (tree type_node) return "__vector_pair"; else if (type_node == vector_quad_type_node) return "__vector_quad"; - else if (type_node == dm1024_type_node) - return "__dm1024"; return "unknown"; } @@ -783,21 +781,6 @@ rs6000_init_builtins (void) t = build_qualified_type (vector_quad_type_node, TYPE_QUAL_CONST); ptr_vector_quad_type_node = build_pointer_type (t); - /* For TDOmode (1,024 bit dense math accumulators), don't use an alignment of - 1,024, use 512. TDOmode loads and stores are always broken up into 2 - vector pair loads or stores. In addition, we don't have support for - aligning the stack to 1,024 bits. */ - dm1024_type_node = make_node (OPAQUE_TYPE); - SET_TYPE_MODE (dm1024_type_node, TDOmode); - TYPE_SIZE (dm1024_type_node) = bitsize_int (GET_MODE_BITSIZE (TDOmode)); - TYPE_PRECISION (dm1024_type_node) = GET_MODE_BITSIZE (TDOmode); - TYPE_SIZE_UNIT (dm1024_type_node) = size_int (GET_MODE_SIZE (TDOmode)); - SET_TYPE_ALIGN (dm1024_type_node, 512); - TYPE_USER_ALIGN (dm1024_type_node) = 0; - lang_hooks.types.register_builtin_type (dm1024_type_node, "__dm1024"); - t = build_qualified_type (dm1024_type_node, TYPE_QUAL_CONST); - ptr_dm1024_type_node = build_pointer_type (t); - tdecl = add_builtin_type ("__bool char", bool_char_type_node); TYPE_NAME (bool_char_type_node) = tdecl; @@ -1142,9 +1125,8 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi, } /* If we're disassembling an accumulator into a different type, we need - to emit a xxmfacc instruction now, since we cannot do it later. If we - have dense math registers, we don't need to do this. */ - if (fncode == RS6000_BIF_DISASSEMBLE_ACC && !TARGET_DENSE_MATH) + to emit a xxmfacc instruction now, since we cannot do it later. */ + if (fncode == RS6000_BIF_DISASSEMBLE_ACC) { new_decl = rs6000_builtin_decls[RS6000_BIF_XXMFACC_INTERNAL]; new_call = gimple_build_call (new_decl, 1, src); diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc index e57162f3b200..e31b147a3b92 100644 --- a/gcc/config/rs6000/rs6000-call.cc +++ b/gcc/config/rs6000/rs6000-call.cc @@ -437,15 +437,14 @@ rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) if (cfun && !cfun->machine->mma_return_type_error && TREE_TYPE (cfun->decl) == fntype - && OPAQUE_MODE_P (TYPE_MODE (type))) + && (TYPE_MODE (type) == OOmode || TYPE_MODE (type) == XOmode)) { /* Record we have now handled function CFUN, so the next time we are called, we do not re-report the same error. */ cfun->machine->mma_return_type_error = true; if (TYPE_CANONICAL (type) != NULL_TREE) type = TYPE_CANONICAL (type); - error ("invalid use of %s type %qs as a function return value", - (TYPE_MODE (type) == TDOmode) ? "dense math" : "MMA", + error ("invalid use of MMA type %qs as a function return value", IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)))); } @@ -1633,12 +1632,11 @@ rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) int n_elts; /* We do not allow MMA types being used as function arguments. */ - if (OPAQUE_MODE_P (mode)) + if (mode == OOmode || mode == XOmode) { if (TYPE_CANONICAL (type) != NULL_TREE) type = TYPE_CANONICAL (type); - error ("invalid use of %s operand of type %qs as a function parameter", - (mode == TDOmode) ? "dense math" : "MMA", + error ("invalid use of MMA operand of type %qs as a function parameter", IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)))); return NULL_RTX; } diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 3e51848481f4..dc67e287672e 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -91,7 +91,6 @@ will be fixed in potential future machines. */ #define FUTURE_MASKS_SERVER (POWER11_MASKS_SERVER \ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ - | OPTION_MASK_DENSE_MATH \ | OPTION_MASK_FUTURE) /* Flags that need to be turned off if -mno-vsx. */ @@ -125,7 +124,6 @@ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ - | OPTION_MASK_DENSE_MATH \ | OPTION_MASK_DFP \ | OPTION_MASK_DLMZB \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index 6fca027949d6..7140b634c414 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -79,7 +79,3 @@ PARTIAL_INT_MODE (TI, 128, PTI); /* Modes used by __vector_pair and __vector_quad. */ OPAQUE_MODE (OO, 32); OPAQUE_MODE (XO, 64); - -/* Mode used by __dmf. */ -OPAQUE_MODE (TDO, 128); - diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 0518e623f252..2587c00301f7 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1843,8 +1843,7 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode) 128-bit floating point that can go in vector registers, which has VSX memory addressing. */ if (FP_REGNO_P (regno)) - reg_size = (VECTOR_MEM_VSX_P (mode) - || VECTOR_ALIGNMENT_P (mode) + reg_size = (VECTOR_MEM_VSX_P (mode) || VECTOR_ALIGNMENT_P (mode) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD); @@ -1898,22 +1897,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) && (regno & 1) == 0); } - if (mode == TDOmode) - { - if (!TARGET_DENSE_MATH) - return 0; - - if (DM_REGNO_P (regno)) - return 1; - - else - return (VSX_REGNO_P (regno) - && VSX_REGNO_P (last_regno) - && (regno & 1) == 0); - } - - /* No other types other than XOmode or TDOmode can go in dense math - registers. */ + /* No other types other than XOmode can go in dense math registers. */ if (DM_REGNO_P (regno)) return 0; @@ -2021,11 +2005,9 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode) GPR registers, and TImode can go in any GPR as well as VSX registers (PR 57744). - Similarly, don't allow OOmode (vector pair), XOmode (vector quad), or - TDOmode (dense math register) to pair with anything else. Vector pairs are - restricted to even/odd VSX registers. Without dense math, vector quads are - limited to FPR registers divisible by 4. With dense math, vector quads are - limited to even VSX registers or dense math registers. + Similarly, don't allow OOmode (vector pair, restricted to even VSX + registers) or XOmode (vector quad, restricted to FPR registers divisible + by 4) to tie with other modes. Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE 128-bit floating point on VSX systems ties with other vectors. */ @@ -2034,8 +2016,7 @@ static bool rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2) { if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode - || mode1 == TDOmode || mode2 == PTImode || mode2 == OOmode - || mode2 == XOmode || mode2 == TDOmode) + || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode) return mode1 == mode2; if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1)) @@ -2326,7 +2307,6 @@ rs6000_debug_reg_global (void) V4DFmode, OOmode, XOmode, - TDOmode, CCmode, CCUNSmode, CCEQmode, @@ -2692,7 +2672,7 @@ rs6000_setup_reg_addr_masks (void) /* Special case dense math registers. */ if (rc == RELOAD_REG_DMR) { - if (TARGET_DENSE_MATH && (m2 == XOmode || m2 == TDOmode)) + if (TARGET_DENSE_MATH && m2 == XOmode) { addr_mask = RELOAD_REG_VALID; reg_addr[m].addr_mask[rc] = addr_mask; @@ -2799,10 +2779,10 @@ rs6000_setup_reg_addr_masks (void) /* Vector pairs can do both indexed and offset loads if the instructions are enabled, otherwise they can only do offset loads - since it will be broken into two vector moves. Vector quads and - dense math types can only do offset loads. */ + since it will be broken into two vector moves. Vector quads can + only do offset loads. */ else if ((addr_mask != 0) && TARGET_MMA - && (m2 == OOmode || m2 == XOmode || m2 == TDOmode)) + && (m2 == OOmode || m2 == XOmode)) { addr_mask |= RELOAD_REG_OFFSET; if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) @@ -3030,14 +3010,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_vector_align[XOmode] = 512; } - /* Add support for 1,024 bit dense math registers. */ - if (TARGET_DENSE_MATH) - { - rs6000_vector_unit[TDOmode] = VECTOR_NONE; - rs6000_vector_mem[TDOmode] = VECTOR_VSX; - rs6000_vector_align[TDOmode] = 512; - } - /* Register class constraints for the constraints that depend on compile switches. When the VSX code was added, different constraints were added based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all @@ -3250,12 +3222,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } } - if (TARGET_DENSE_MATH) - { - reg_addr[TDOmode].reload_load = CODE_FOR_reload_tdo_from_memory; - reg_addr[TDOmode].reload_store = CODE_FOR_reload_tdo_to_memory; - } - /* Precalculate HARD_REGNO_NREGS. */ for (r = 0; HARD_REGISTER_NUM_P (r); ++r) for (m = 0; m < NUM_MACHINE_MODES; ++m) @@ -8769,15 +8735,12 @@ reg_offset_addressing_ok_p (machine_mode mode) return mode_supports_dq_form (mode); break; - /* The vector pair/quad types and the dense math types support offset - addressing if the underlying vectors support offset addressing. */ + /* The vector pair/quad types support offset addressing if the + underlying vectors support offset addressing. */ case E_OOmode: case E_XOmode: return TARGET_MMA; - case E_TDOmode: - return TARGET_DENSE_MATH; - case E_SDmode: /* If we can do direct load/stores of SDmode, restrict it to reg+reg addressing for the LFIWZX and STFIWX instructions. */ @@ -11331,12 +11294,6 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode) (mode == OOmode) ? "__vector_pair" : "__vector_quad"); break; - case E_TDOmode: - if (CONST_INT_P (operands[1])) - error ("%qs is an opaque type, and you cannot set it to constants", - "__dm1024"); - break; - case E_SImode: case E_DImode: /* Use default pattern for address of ELF small data */ @@ -12800,7 +12757,7 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type, /* We can transfer between VSX registers and dense math registers without needing extra registers. */ - if (TARGET_DENSE_MATH && (mode == XOmode || mode == TDOmode) + if (TARGET_DENSE_MATH && mode == XOmode && ((to_type == DM_REG_TYPE && from_type == VSX_REG_TYPE) || (to_type == VSX_REG_TYPE && from_type == DM_REG_TYPE))) return true; @@ -13601,9 +13558,6 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) if (mode == XOmode) return TARGET_DENSE_MATH ? VSX_REGS : FLOAT_REGS; - if (mode == TDOmode) - return VSX_REGS; - if (GET_MODE_CLASS (mode) == MODE_INT) return GENERAL_REGS; } @@ -20778,8 +20732,6 @@ rs6000_mangle_type (const_tree type) return "u13__vector_pair"; if (type == vector_quad_type_node) return "u13__vector_quad"; - if (type == dm1024_type_node) - return "u8__dm1024"; /* For all other types, use the default mangling. */ return NULL; @@ -22910,10 +22862,6 @@ rs6000_dense_math_register_move_cost (machine_mode mode, reg_class_t rclass) if (mode == XOmode) return reg_move_base; - /* __dm1024 (i.e. TDOmode) is transferred in 2 instructions. */ - else if (mode == TDOmode) - return reg_move_base * 2; - else return reg_move_base * 2 * hard_regno_nregs (FIRST_DM_REGNO, mode); } @@ -27600,10 +27548,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) mode = GET_MODE (dst); nregs = hard_regno_nregs (reg, mode); - /* If we have a vector quad register for MMA or dense math register - and this is a load or store, see if we can use vector paired - load/stores. */ - if ((mode == XOmode || mode == TDOmode) && TARGET_MMA + /* If we have a vector quad register for MMA, and this is a load or store, + see if we can use vector paired load/stores. */ + if (mode == XOmode && TARGET_MMA && (MEM_P (dst) || MEM_P (src))) { reg_mode = OOmode; @@ -27611,7 +27558,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) } /* If we have a vector pair/quad mode, split it into two/four separate vectors. */ - else if (mode == OOmode || mode == XOmode || mode == TDOmode) + else if (mode == OOmode || mode == XOmode) reg_mode = V1TImode; else if (FP_REGNO_P (reg)) reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : @@ -27657,13 +27604,13 @@ rs6000_split_multireg_move (rtx dst, rtx src) return; } - /* The __vector_pair, __vector_quad, and __dm1024 modes are multi-register - modes, so if we have to load or store the registers, we have to be careful - to properly swap them if we're in little endian mode below. This means - the last register gets the first memory location. We also need to be - careful of using the right register numbers if we are splitting XO to - OO. */ - if (mode == OOmode || mode == XOmode || mode == TDOmode) + /* The __vector_pair and __vector_quad modes are multi-register + modes, so if we have to load or store the registers, we have to be + careful to properly swap them if we're in little endian mode + below. This means the last register gets the first memory + location. We also need to be careful of using the right register + numbers if we are splitting XO to OO. */ + if (mode == OOmode || mode == XOmode) { nregs = hard_regno_nregs (reg, mode); int reg_mode_nregs = hard_regno_nregs (reg, reg_mode); @@ -27800,7 +27747,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) overlap. */ int i; /* XO/OO are opaque so cannot use subregs. */ - if (mode == OOmode || mode == XOmode || mode == TDOmode) + if (mode == OOmode || mode == XOmode ) { for (i = nregs - 1; i >= 0; i--) { @@ -27974,7 +27921,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) continue; /* XO/OO are opaque so cannot use subregs. */ - if (mode == OOmode || mode == XOmode || mode == TDOmode) + if (mode == OOmode || mode == XOmode ) { rtx dst_i = gen_rtx_REG (reg_mode, REGNO (dst) + j); rtx src_i = gen_rtx_REG (reg_mode, REGNO (src) + j); @@ -29002,8 +28949,7 @@ rs6000_invalid_conversion (const_tree fromtype, const_tree totype) if (frommode != tomode) { - /* Do not allow conversions to/from XOmode, OOmode, and TDOmode - types. */ + /* Do not allow conversions to/from XOmode and OOmode types. */ if (frommode == XOmode) return N_("invalid conversion from type %<__vector_quad%>"); if (tomode == XOmode) @@ -29012,10 +28958,6 @@ rs6000_invalid_conversion (const_tree fromtype, const_tree totype) return N_("invalid conversion from type %<__vector_pair%>"); if (tomode == OOmode) return N_("invalid conversion to type %<__vector_pair%>"); - if (frommode == TDOmode) - return N_("invalid conversion from type %<__dm1024%>"); - if (tomode == TDOmode) - return N_("invalid conversion to type %<__dm1024%>"); } /* Conversion allowed. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 6ba75af461e6..5214a7c22cea 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -983,7 +983,7 @@ enum data_align { align_abi, align_opt, align_both }; /* Modes that are not vectors, but require vector alignment. Treat these like vectors in terms of loads and stores. */ #define VECTOR_ALIGNMENT_P(MODE) \ - (FLOAT128_VECTOR_P (MODE) || OPAQUE_MODE_P (MODE)) + (FLOAT128_VECTOR_P (MODE) || (MODE) == OOmode || (MODE) == XOmode) #define ALTIVEC_VECTOR_MODE(MODE) \ ((MODE) == V16QImode \ @@ -2274,7 +2274,6 @@ enum rs6000_builtin_type_index RS6000_BTI_const_str, /* pointer to const char * */ RS6000_BTI_vector_pair, /* unsigned 256-bit types (vector pair). */ RS6000_BTI_vector_quad, /* unsigned 512-bit types (vector quad). */ - RS6000_BTI_dm1024, /* unsigned 1,024-bit types (dmf). */ RS6000_BTI_const_ptr_void, /* const pointer to void */ RS6000_BTI_ptr_V16QI, RS6000_BTI_ptr_V1TI, @@ -2313,7 +2312,6 @@ enum rs6000_builtin_type_index RS6000_BTI_ptr_dfloat128, RS6000_BTI_ptr_vector_pair, RS6000_BTI_ptr_vector_quad, - RS6000_BTI_ptr_dm1024, RS6000_BTI_ptr_long_long, RS6000_BTI_ptr_long_long_unsigned, RS6000_BTI_MAX @@ -2371,7 +2369,6 @@ enum rs6000_builtin_type_index #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) #define vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_vector_pair]) #define vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_vector_quad]) -#define dm1024_type_node (rs6000_builtin_types[RS6000_BTI_dm1024]) #define pcvoid_type_node (rs6000_builtin_types[RS6000_BTI_const_ptr_void]) #define ptr_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V16QI]) #define ptr_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V1TI]) @@ -2410,7 +2407,6 @@ enum rs6000_builtin_type_index #define ptr_dfloat128_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat128]) #define ptr_vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_pair]) #define ptr_vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_quad]) -#define ptr_dm1024_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dm1024]) #define ptr_long_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long]) #define ptr_long_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long_unsigned]) diff --git a/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c b/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c deleted file mode 100644 index c75a2b3bcd35..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/dm-1024bit.c +++ /dev/null @@ -1,63 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_dense_math_ok } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -/* Test basic load/store for __dm1024 type. */ - -#ifndef CONSTRAINT -#if defined(USE_D) -#define CONSTRAINT "d" - -#elif defined(USE_V) -#define CONSTRAINT "v" - -#elif defined(USE_WA) -#define CONSTRAINT "wa" - -#else -#define CONSTRAINT "wD" -#endif -#endif -const char constraint[] = CONSTRAINT; - -void foo_mem_asm (__dm1024 *p, __dm1024 *q) -{ - /* 2 LXVP instructions. */ - __dm1024 vq = *p; - - /* 2 DMXXINSTDMR512 instructions to transfer VSX to dense math register. */ - __asm__ ("# foo (" CONSTRAINT ") %A0" : "+" CONSTRAINT (vq)); - /* 2 DMXXEXTFDMR512 instructions to transfer dense math register to VSX. */ - - /* 2 STXVP instructions. */ - *q = vq; -} - -void foo_mem_asm2 (__dm1024 *p, __dm1024 *q) -{ - /* 2 LXVP instructions. */ - __dm1024 vq = *p; - __dm1024 vq2; - __dm1024 vq3; - - /* 2 DMXXINSTDMR512 instructions to transfer VSX to dense math register. */ - __asm__ ("# foo1 (" CONSTRAINT ") %A0" : "+" CONSTRAINT (vq)); - /* 2 DMXXEXTFDMR512 instructions to transfer dense math register to VSX. */ - - vq2 = vq; - __asm__ ("# foo2 (wa) %0" : "+wa" (vq2)); - - /* 2 STXVP instructions. */ - *q = vq2; -} - -void foo_mem (__dm1024 *p, __dm1024 *q) -{ - /* 2 LXVP, 2 STXVP instructions, no dense math transfer. */ - *q = *p; -} - -/* { dg-final { scan-assembler-times {\mdmxxextfdmr512\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mdmxxinstdmr512\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mlxvp\M} 12 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 12 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-dm-1.c b/gcc/testsuite/gcc.target/powerpc/mma-dm-1.c deleted file mode 100644 index 8f534e76d233..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/mma-dm-1.c +++ /dev/null @@ -1,67 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_future_ok } */ -/* { dg-options "-mdejagnu-cpu=future -O2" } */ - -/* Test basic dense math support for MMA. */ - -void -move_simple (__vector_quad *a, __vector_quad *b) -{ - /* 2 lxvp, 2 stxvp. */ - __vector_quad c = *a; - *b = c; -} - -void -move_constraint_d (__vector_quad *a, __vector_quad *b) -{ - /* 2 lxvp, 2 stxvp. */ - __vector_quad c = *a; - __asm__ (" # %x0 (d constraint)" : "+d" (c)); - *b = c; -} - -void -move_constraint_wD (__vector_quad *a, __vector_quad *b) -{ - /* 2 lxvp, dmxxinstdmr512, dmxxextfdmr512, 2 stxvp. */ - __vector_quad c = *a; - __asm__ (" # %A0 (wD constraint)" : "+wD" (c)); - *b = c; -} - -void -clear_simple (__vector_quad *a) -{ - /* dmsetdmrz, dmxxextfdmr512, 2 stxvp. */ - __builtin_mma_xxsetaccz (a); -} - -void -clear_constraint_d (__vector_quad *a) -{ - __vector_quad z; - - /* dmsetdmrz, dmxxextfdmr512, 2 stxvp. */ - __builtin_mma_xxsetaccz (&z); - __asm__ (" # %x0 (d constraint)" : "+d" (z)); - *a = z; -} - -void -clear_constraint_wD (__vector_quad *a) -{ - __vector_quad z; - - /* dmsetdmrz, dmxxextfdmr512, 2 stxvp. */ - __builtin_mma_xxsetaccz (&z); - __asm__ (" # %A0 (d constraint)" : "+wD" (z)); - *a = z; -} - -/* { dg-final { scan-assembler-times {\mdmsetdmrz\M} 3 } } */ -/* { dg-final { scan-assembler-times {\mdmxxextfdmr512\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mdmxxinstdmr512\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mxxmfacc\M} } } */ -/* { dg-final { scan-assembler-not {\mxxmtacc\M} } } */ -/* { dg-final { scan-assembler-not {\mxxsetaccz\M } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-dm-2.c b/gcc/testsuite/gcc.target/powerpc/mma-dm-2.c deleted file mode 100644 index 2ac1b4da330d..000000000000 --- a/gcc/testsuite/gcc.target/powerpc/mma-dm-2.c +++ /dev/null @@ -1,67 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target powerpc_dense_math_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -mno-dense-math -O2" } */ - -/* Test basic dense math support for MMA. */ - -void -move_simple (__vector_quad *a, __vector_quad *b) -{ - /* 2 lxvp, xxmtacc, xxftacc 2 stxvp. */ - __vector_quad c = *a; - *b = c; -} - -void -move_constraint_d (__vector_quad *a, __vector_quad *b) -{ - /* 2 lxvp, xxmtacc, xxftacc, 2 stxvp. */ - __vector_quad c = *a; - __asm__ (" # %x0 (d constraint)" : "+d" (c)); - *b = c; -} - -void -move_constraint_wD (__vector_quad *a, __vector_quad *b) -{ - /* 2 lxvp, xxmtacc, xxftacc, 2 stxvp. */ - __vector_quad c = *a; - __asm__ (" # %A0 (wD constraint)" : "+wD" (c)); - *b = c; -} - -void -clear_simple (__vector_quad *a) -{ - /* xxsetaccz, xxmfacc, 2 stxvp. */ - __builtin_mma_xxsetaccz (a); -} - -void -clear_constraint_d (__vector_quad *a) -{ - __vector_quad z; - - /* xxsetaccz, xxmfacc, 2 stxvp. */ - __builtin_mma_xxsetaccz (&z); - __asm__ (" # %x0 (d constraint)" : "+d" (z)); - *a = z; -} - -void -clear_constraint_wD (__vector_quad *a) -{ - __vector_quad z; - - /* xxsetaccz, xxmfacc, 2 stxvp. */ - __builtin_mma_xxsetaccz (&z); - __asm__ (" # %A0 (d constraint)" : "+wD" (z)); - *a = z; -} - -/* { dg-final { scan-assembler-not {\mdmsetdmrz\M} } } */ -/* { dg-final { scan-assembler-not {\mdmxxextfdmr512\M} } } */ -/* { dg-final { scan-assembler-not {\mdmxxinstdmr512\M} } } */ -/* { dg-final { scan-assembler-times {\mxxmfacc\M} 6 } } */ -/* { dg-final { scan-assembler-times {\mxxmtacc\M} 3 } } */ -/* { dg-final { scan-assembler-times {\mxxsetaccz\M 3 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index dba4a9a2936c..c87918275569 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -7989,41 +7989,6 @@ proc check_effective_target_power10_ok { } { } } -# Return 1 if this is a PowerPC target supporting -mcpu=future which enables -# some potential new instructions. -proc check_effective_target_powerpc_future_ok { } { - return [check_no_compiler_messages powerpc_future_ok object { - #ifndef _ARCH_PWR_FUTURE - #error "-mcpu=future is not supported" - #else - int dummy; - #endif - } "-mcpu=future"] -} - -# Return 1 if this is a PowerPC target supporting -mcpu=future which enables -# the dense math operations. -proc check_effective_target_powerpc_dense_math_ok { } { - if { ([istarget powerpc*-*-*]) } { - return [check_no_compiler_messages powerpc_dense_math_ok object { - __vector_quad vq; - int main (void) { - #ifndef __DENSE_MATH__ - #error "target does not have dense math support." - #else - /* Make sure we have dense math support. */ - __vector_quad dmr; - __asm__ ("dmsetaccz %A0" : "=wD" (dmr)); - vq = dmr; - #endif - return 0; - } - } "-mcpu=future"] - } else { - return 0; - } -} - # Return 1 if this is a PowerPC target supporting -mfloat128 via either # software emulation on power7/power8 systems or hardware support on power9.
