https://gcc.gnu.org/g:b34e2e2b2c47f44f6f7a68cd22b965ad1da9813c
commit b34e2e2b2c47f44f6f7a68cd22b965ad1da9813c Author: Michael Meissner <[email protected]> Date: Tue May 12 22:51:20 2026 -0400 Add xvrlw support. This patch adds support for a possible new variant of the vector rotate left instruction that might be added to a future PowerPC. This variant (xvrlw) can use any VSX register instead of requiring only Altivec registers. As a potential test, add other variants of vxvrl<x> enabled with the -mxvrld option. 2026-05-07 Michael Meissner <[email protected]> gcc/ * config/rs6000/altivec.md (xvrlw): New insn. (test_xvrl<VI_char>): Add test insns. * config/rs6000/rs6000.h (TARGET_XVRLD): New macro. gcc/testsuite/ * gcc.target/powerpc/vector-rotate-left.c: New test. Diff: --- gcc/config/rs6000/altivec.md | 25 ++++++++++++++++ gcc/config/rs6000/rs6000.h | 3 ++ gcc/config/rs6000/rs6000.opt | 4 +++ .../gcc.target/powerpc/vector-rotate-left.c | 34 ++++++++++++++++++++++ 4 files changed, 66 insertions(+) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 129f56245cd0..b7f99e04e7b6 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1982,6 +1982,31 @@ } [(set_attr "type" "vecperm")]) +;; -mcpu=future adds a vector rotate left word variant. There is no vector +;; byte/half-word/double-word/quad-word rotate left. This insn occurs before +;; altivec_vrl<VI_char> and will match for -mcpu=future, while other cpus will +;; match the generic insn. +(define_insn "*xvrlw" + [(set (match_operand:V4SI 0 "register_operand" "=v,wa") + (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa") + (match_operand:V4SI 2 "register_operand" "v,wa")))] + "TARGET_XVRLW" + "@ + vrlw %0,%1,%2 + xvrlw %x0,%x1,%x2" + [(set_attr "type" "vecsimple")]) + +;; Add a test for the other vector rotate instructions also. +(define_insn "*test_xvrl<VI_char>" + [(set (match_operand:VI2 0 "register_operand" "=v,wa") + (rotate:VI2 (match_operand:VI2 1 "register_operand" "v,wa") + (match_operand:VI2 2 "register_operand" "v,wa")))] + "TARGET_XVRLD && <MODE>mode != V4SImode" + "@ + vrl<VI_char> %0,%1,%2 + xvrl<VI_char> %x0,%x1,%x2" + [(set_attr "type" "vecsimple")]) + (define_insn "altivec_vrl<VI_char>" [(set (match_operand:VI2 0 "register_operand" "=v") (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3f9c55bc2f8f..ac3944757e53 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -565,6 +565,9 @@ extern int rs6000_vector_align[]; below. */ #define RS6000_FN_TARGET_INFO_HTM 1 +/* Whether we have XVRLW support. */ +#define TARGET_XVRLW TARGET_FUTURE + /* Whether the various reciprocal divide/square root estimate instructions exist, and whether we should automatically generate code for the instruction by default. */ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 2b6ec5222fc1..049fb23d349e 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -638,6 +638,10 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. +mxvrld +Target Var(TARGET_XVRLD) Init(0) Save +Generate (do not generate) code that uses the potential XVRL{B,H,D} instructions. + ; Documented parameters -param=rs6000-vect-unroll-limit= diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c new file mode 100644 index 000000000000..f9e87ad4bfcf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_future_ok } */ +/* { dg-options "-mdejagnu-cpu=future -O2" } */ + +/* Test whether the xvrl (vector word rotate left using VSX registers insead of + Altivec registers is generated. */ + +#include <altivec.h> + +typedef vector unsigned int v4si_t; + +v4si_t +rotl_v4si_scalar (v4si_t x, unsigned long n) +{ + __asm__ (" # %x0" : "+f" (x)); + return (x << n) | (x >> (32 - n)); /* xvrlw. */ +} + +v4si_t +rotr_v4si_scalar (v4si_t x, unsigned long n) +{ + __asm__ (" # %x0" : "+f" (x)); + return (x >> n) | (x << (32 - n)); /* xvrlw. */ +} + +v4si_t +rotl_v4si_vector (v4si_t x, v4si_t y) +{ + __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */ + return vec_rl (x, y); +} + +/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */ +/* { dg-final { scan-assembler-not {\mvrlw\M} } } */
