https://gcc.gnu.org/g:8b2102ff9c55f0834eab7016f2bc9b272dea2085
commit r15-11537-g8b2102ff9c55f0834eab7016f2bc9b272dea2085 Author: Peter Bergner <[email protected]> Date: Mon Aug 31 21:09:16 2026 +0000 riscv: Add -mcpu= and -mtune = support for tt-ascalon-x The Ascalon cpu's official marketing name is Ascalon X. Add support for the -mcpu= and -mtune= options to accept tt-ascalon-x as the cpu's name in addition to the older tt-ascalon-d8 name. 2026-06-25 Peter Bergner <[email protected]> gcc/ * config/riscv/riscv-cores.def (RISCV_TUNE): Add tt-ascalon-x. (RISCV_CORE): Likewise. * doc/invoke.texi: Document it. Signed-off-by: Peter Bergner <[email protected]> (cherry picked from commit cda406c44f12945f530c79497f29c6784904bc57) Diff: --- gcc/config/riscv/riscv-cores.def | 9 +++++++++ gcc/doc/invoke.texi | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index a258a240dde0..b2672cd233d7 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -39,6 +39,7 @@ RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) +RISCV_TUNE("tt-ascalon-x", generic_ooo, tt_ascalon_d8_tune_info) RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) @@ -93,6 +94,14 @@ RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadmemidx_xtheadmempair_xtheadsync", "thead-c906") +RISCV_CORE("tt-ascalon-x", "rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_" + "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_" + "zifencei_zihintntl_zihintpause_zimop_za64rs_" + "zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_" + "zvbb_zvbc_zvfbfmin_zvfbfwma_zvfh_zvkng_zvl256b_" + "zfhmin_zicntr_zihpm_zkr_zkt_zvfhmin_zvkt", + "tt-ascalon-x") + RISCV_CORE("tt-ascalon-d8", "rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_" "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_" "zifencei_zihintntl_zihintpause_zimop_za64rs_" diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8c38abf1ac4f..49a376cb5991 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31616,7 +31616,7 @@ Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76}, @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450}, -@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8}, +@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-x}, @samp{tt-ascalon-d8}, @samp{xiangshan-nanhu}. Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}.
