https://gcc.gnu.org/g:045a310763b2609ea69c81fb270955dace7cb0f1
commit r15-11538-g045a310763b2609ea69c81fb270955dace7cb0f1 Author: Peter Bergner <[email protected]> Date: Mon Aug 31 21:12:08 2026 +0000 RISC-V: Add Ascalon XG cpu support This adds support for the global version of Ascalon X (tt-ascalon-xg) to the list of known cores. The difference between Ascalon X & XG is XG does not have the zvkng extension and it has reduced vector FP64 throughput. 2026-08-12 Peter Bergner <[email protected]> gcc/ * config/riscv/riscv-cores.def (RISCV_TUNE): Add tt-ascalon-xg. (RISCV_CORE): Likewise. * doc/invoke.texi: Document it. Signed-off-by: Peter Bergner <[email protected]> (cherry picked from commit b96b7700184c080d3a72a608e0e7115108b14ac1) Diff: --- gcc/config/riscv/riscv-cores.def | 9 +++++++++ gcc/doc/invoke.texi | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index b2672cd233d7..58d8e7d995de 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -41,6 +41,7 @@ RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) RISCV_TUNE("tt-ascalon-x", generic_ooo, tt_ascalon_d8_tune_info) RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info) +RISCV_TUNE("tt-ascalon-xg", generic_ooo, tt_ascalon_d8_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) @@ -110,6 +111,14 @@ RISCV_CORE("tt-ascalon-d8", "rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_" "zfhmin_zicntr_zihpm_zkr_zkt_zvfhmin_zvkt", "tt-ascalon-d8") +RISCV_CORE("tt-ascalon-xg", "rv64imafdcbv_zic64b_zicbom_zicbop_zicboz_" + "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_" + "zifencei_zihintntl_zihintpause_zimop_za64rs_" + "zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_" + "zvbb_zvbc_zvfbfmin_zvfbfwma_zvfh_zvl256b_" + "zfhmin_zicntr_zihpm_zkr_zkt_zvfhmin_zvkt", + "tt-ascalon-xg") + RISCV_CORE("xiangshan-nanhu", "rv64imafdc_zba_zbb_zbc_zbs_" "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_" "svinval_zicbom_zicboz", diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 49a376cb5991..f281e4eb9afb 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31617,7 +31617,7 @@ Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76}, @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450}, @samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-x}, @samp{tt-ascalon-d8}, -@samp{xiangshan-nanhu}. +@samp{tt-ascalon-xg}, @samp{xiangshan-nanhu}. Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}.
