gcc-cvs  

Messages by Thread

• • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] dep_fusion: Fix if target does not have macro fusion [PR121835] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesvsintload ISA extension. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesvsintload ISA extension. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesvbfhcvt ISA extension. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesvbfhcvt ISA extension. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add tt-ascalon-d8 pipeline description Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add tt-ascalon-d8 pipeline description Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2VR cost Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2VR cost Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Allow errors to be suppressed when parsing architectures Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Allow errors to be suppressed when parsing architectures Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmadd.vv unsigned combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmadd.vv unsigned combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust the vmacc.vx combine test cases Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adjust the vmacc.vx combine test cases Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmadd.vv signed combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmadd.vv signed combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix extension subset check in riscv_can_inline_p Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix extension subset check in riscv_can_inline_p Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesperf ISA extension. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesperf ISA extension. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesbfhcvt ISA extension. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for the XAndesbfhcvt ISA extension. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add basic XAndes vendor extension support. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add basic XAndes vendor extension support. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix is_vlmax_len_p and use for strided ops. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix is_vlmax_len_p and use for strided ops. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Zbb extension sext testcase. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add Zbb extension sext testcase. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update Zba 'shNadd.uw' testcase.` Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update Zba 'shNadd.uw' testcase.` Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove unused print_ext_doc_entry function [NFC] Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove unused print_ext_doc_entry function [NFC] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve initial RTL generation for SImode adds on rv64 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Improve initial RTL generation for SImode adds on rv64 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for unsigned scalar SAT_MUL form 4 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for unsigned scalar SAT_MUL form 4 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add patterns for vector-scalar IEEE floating-point min Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add patterns for vector-scalar IEEE floating-point min Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vnmsac.vv signed combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vnmsac.vv signed combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on GR2VR cost Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on GR2VR cost Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pattern for vector-scalar floating-point min Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add pattern for vector-scalar floating-point min Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Remove xfail marker on RISC-V test Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Remove xfail marker on RISC-V test Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed] RISC-V Testsuite hygiene Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [committed] RISC-V Testsuite hygiene Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] More RISC-V testsuite hygiene Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] More RISC-V testsuite hygiene Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Add pattern for vector-scalar single-width floating-point multiply Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Add pattern for vector-scalar single-width floating-point multiply Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Add pattern for reverse floating-point divide Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Add pattern for reverse floating-point divide Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Fix RISC-V bootstrap Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Fix RISC-V bootstrap Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmacc.vv unsigned combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmacc.vv unsigned combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmacc.vv signed combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vmacc.vv signed combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2VR cost Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2VR cost Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE macros with target hooks Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE macros with target hooks Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Fix invalid right shift count with recent ifcvt changes Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Fix invalid right shift count with recent ifcvt changes Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PR rtl-optimization/120553] Improve selecting between constants based on sign bit test Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PR rtl-optimization/120553] Improve selecting between constants based on sign bit test Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for scalar unsigned SAT_MUL form 3 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for scalar unsigned SAT_MUL form 3 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PR target/121213] Avoid unnecessary constant load in amoswap Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PR target/121213] Avoid unnecessary constant load in amoswap Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] regrename: treat writes as reads for fused instruction pairs Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] regrename: treat writes as reads for fused instruction pairs Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] ira: tie output allocnos for fused instruction pairs Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] ira: tie output allocnos for fused instruction pairs Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR121538] Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR121538] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update the comments of vx combine [NFC] Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Update the comments of vx combine [NFC] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add missed DONE for vx combine pattern [NFC] Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add missed DONE for vx combine pattern [NFC] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PR target/119275][RISC-V] Avoid calling gen_lowpart in cases where it would ICE Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PR target/119275][RISC-V] Avoid calling gen_lowpart in cases where it would ICE Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/121531] Cover missing insn types in p400 and p600 scheduler models Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/121531] Cover missing insn types in p400 and p600 scheduler models Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/121160] Avoid bogus force_reg call Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/121160] Avoid bogus force_reg call Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/121113] Handle HFmode in various insn reservations Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V][PR target/121113] Handle HFmode in various insn reservations Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm combine with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on GR2VR cost Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on GR2VR cost Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Improve initial code generation for addsi/adddi Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Improve initial code generation for addsi/adddi Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Expand const_vector with 2 elts per pattern. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Expand const_vector with 2 elts per pattern. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Don't run tests requiring "B" on designs without "B" Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Don't run tests requiring "B" on designs without "B" Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for scalar unsigned SAT_MUL form 2 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for scalar unsigned SAT_MUL form 2 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost param Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost param Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix scalar code-gen of unsigned SAT_MUL Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix scalar code-gen of unsigned SAT_MUL Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Read extension data from riscv-ext*.def for arch-canonicalize Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Read extension data from riscv-ext*.def for arch-canonicalize Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for signed avg ceil vx combine Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for signed avg ceil vx combine Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support -march=unset Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support -march=unset Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding H to the canonical order [PR121312] Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Adding H to the canonical order [PR121312] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for unsigned avg ceil vx combine. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for unsigned avg ceil vx combine. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaadd.vv combine case 0 with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaadd.vv combine case 0 with GR2VR cost 0, 1 and 15 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Generate -mcpu and -mtune options from riscv-cores.def. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Generate -mcpu and -mtune options from riscv-cores.def. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove use of structured binding to fix compiler warning Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove use of structured binding to fix compiler warning Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: riscv-ext.def: Add allocated group IDs and group bit positions Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: riscv-ext.def: Add allocated group IDs and group bit positions Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for mul based unsigned scalar SAT_MUL Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test cases for mul based unsigned scalar SAT_MUL Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for vaadd.vx combine polluting VXRM Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for vaadd.vx combine polluting VXRM Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaadd.vv combine case 1 with GR2VR cost 0, 1 and 2 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove user-level interrupts Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Remove user-level interrupts Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for resumable non-maskable interrupt (RNMI) handlers Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add support for resumable non-maskable interrupt (RNMI) handlers Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] riscv: testsuite: Fix misalignment check. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] riscv: testsuite: Fix misalignment check. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix another vf FP16 combine run test failures Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix another vf FP16 combine run test failures Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Prepare dynamic LMUL heuristic for SLP. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Prepare dynamic LMUL heuristic for SLP. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rework broadcast handling [PR121073]. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Rework broadcast handling [PR121073]. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for vx combine polluting VXRM Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test case for vx combine polluting VXRM Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Restrict generic-vector-ooo DFA Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [RISC-V] Restrict generic-vector-ooo DFA Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Change bellow in comments to below Jeff Law via Libstdc++-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] Change bellow in comments to below Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine for DImode Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Allow VLS DImode for sat_op vx DImode pattern Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Allow VLS DImode for sat_op vx DImode pattern Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 1 with GR2VR cost 0, 1 and 2 for QI, HI Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add test for vec_duplicate + vaaddu.vv combine case 0 with GR2VR cost 0, 2 and 15 for QI, HI Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on GR2VR cost for HI, QI and SI mode Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and form 9 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC] Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p () Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro_fusion_pair_p () Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg_ceil Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100] Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix vsetvl merge rule. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Fix vsetvl merge rule. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RVVDImode for avg3_ceil auto vect Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RVVDImode for avg3_ceil auto vect Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v5] RISC-V: Mips P8700 Conditional Move Support. Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v5] RISC-V: Mips P8700 Conditional Move Support. Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RVVDImode for avg3_floor auto vect Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Support RVVDImode for avg3_floor auto vect Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for rv32 SAT_MUL from uint64 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcase for rv32 SAT_MUL from uint64 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12 Jeff Law via Gcc-cvs
  • [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Add testcases for unsigned vector SAT_SUB form 11 and form 12 Jeff Law via Gcc-cvs
• [gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Make zero-stride load broadcast a tunable. Jeff Law via Gcc-cvs

• Earlier messages
• Later messages