On 05/23/2011 07:05 PM, Joseph S. Myers wrote:
On Mon, 23 May 2011, Aldy Hernandez wrote:
This is a patch implementing builtins for an atomic exchange with full,
acquire, and release memory barrier semantics. It is similar to
__sync_lock_test_and_set(), but the target does not have the option of
implementing a reduced functionality of only implementing a store of 1. Also,
unlike __sync_lock_test_and_set(), we have all three memory barrier variants.
What's the reason you've implemented three variants, rather than six (the
C1X/C++0X atomics have six memory order values) or one built-in function
taking a memory order parameter? More generally, what is the underlying
design here for how built-in functions should cover the whole of the new
atomics functionality in C1X and C++0X?
Aldy was just too excited about working on memory model I think :-)
I've been looking at this, and I propose we go this way :
http://gcc.gnu.org/wiki/Atomic/GCCMM/CodeGen
Please feel free to criticize, comment on, or ask for clarification. I
usually miss something I meant to get across.
Andrew
