Following backport tested on 4.8/4.9 with no new regressions. Ok to
commit to those branches?
-Pat
2015-01-12 Pat Haugen <pthau...@us.ibm.com>
Backport from mainline
2014-12-20 Segher Boessenkool <seg...@kernel.crashing.org>
PR target/64358
* config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the
input operands if only the second is inverted.
* config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128):
Swap BOOL_REGS_OP1 and BOOL_REGS_OP2. Correct arguments to
rs6000_split_logical.
(*boolc<mode>3_internal2 for TI2): Swap operands[1] and
operands[2].
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 219474)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -32553,6 +32553,14 @@ rs6000_split_logical_inner (rtx dest,
if (complement_op2_p)
op2 = gen_rtx_NOT (mode, op2);
+ /* For canonical RTL, if only one arm is inverted it is the first. */
+ if (!complement_op1_p && complement_op2_p)
+ {
+ rtx temp = op1;
+ op1 = op2;
+ op2 = temp;
+ }
+
bool_rtx = ((code == NOT)
? gen_rtx_NOT (mode, op1)
: gen_rtx_fmt_ee (code, mode, op1, op2));
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 219474)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -8600,8 +8600,8 @@ (define_insn_and_split "*boolc<mode>3_in
[(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
(match_operator:BOOL_128 3 "boolean_operator"
[(not:BOOL_128
- (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
- (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
"TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
{
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
@@ -8616,7 +8616,7 @@ (define_insn_and_split "*boolc<mode>3_in
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true,
NULL_RTX);
DONE;
}
@@ -8638,14 +8638,14 @@ (define_insn_and_split "*boolc<mode>3_in
[(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
(match_operator:TI2 3 "boolean_operator"
[(not:TI2
- (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
- (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
+ (match_operand:TI2 2 "int_reg_operand" "r,0,r"))
+ (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
"!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
"#"
"reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true,
NULL_RTX);
DONE;
}
