If rs6000_split_logical is asked to invert the second operand (but not
the first), it emits RTL that is just that; but canonical RTL has the
first arm inverted if only one, not the second. This patch fixes that.
With that in place, the bug in PR target/64358 is easily fixed. Do
that. Also change the other 128-bit boolc splitter to have the same
operand order as everything else. And use BOOL_REGS_OP1 and _OP2 for
operands 1 resp. 2 (not the other way around); this doesn't actually
matter, but it was a bit confusing.
This fixes builtin-arith-overflow-{10,11}.c as well.
Bootstrapped (no fortran this time, it doesn't build right now) and
tested on powerpc64-linux, -m32,-m32/-mpowerpc64,-m64,-m64/-mlra; no
regressions (and the mentioned cases fixed).
Okay for mainline? Does this need backporting as well?
Segher
2014-12-20 Segher Boessenkool <seg...@kernel.crashing.org>
gcc/
PR target/64358
* config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the
input operands if only the second is inverted.
* config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128):
Swap BOOL_REGS_OP1 and BOOL_REGS_OP2. Correct arguments to
rs6000_split_logical.
(*boolc<mode>3_internal2 for TI2): Swap operands[1] and operands[2].
---
gcc/config/rs6000/rs6000.c | 4 ++++
gcc/config/rs6000/rs6000.md | 12 ++++++------
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 73152ce..bbed888 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -33167,6 +33167,10 @@ rs6000_split_logical_inner (rtx dest,
if (complement_op2_p)
op2 = gen_rtx_NOT (mode, op2);
+ /* For canonical RTL, if only one arm is inverted it is the first. */
+ if (!complement_op1_p && complement_op2_p)
+ std::swap (op1, op2);
+
bool_rtx = ((code == NOT)
? gen_rtx_NOT (mode, op1)
: gen_rtx_fmt_ee (code, mode, op1, op2));
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 36e6182..2d3a5d3 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7570,8 +7570,8 @@ (define_insn_and_split "*boolc<mode>3_internal1"
[(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
(match_operator:BOOL_128 3 "boolean_operator"
[(not:BOOL_128
- (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
- (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
+ (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
+ (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
"TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
{
if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
@@ -7586,7 +7586,7 @@ (define_insn_and_split "*boolc<mode>3_internal1"
&& reload_completed && int_reg_operand (operands[0], <MODE>mode)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
DONE;
}
[(set (attr "type")
@@ -7607,14 +7607,14 @@ (define_insn_and_split "*boolc<mode>3_internal2"
[(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
(match_operator:TI2 3 "boolean_operator"
[(not:TI2
- (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
- (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
+ (match_operand:TI2 2 "int_reg_operand" "r,0,r"))
+ (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
"!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
"#"
"reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
[(const_int 0)]
{
- rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
+ rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
DONE;
}
[(set_attr "type" "integer")
--
1.8.1.4
