On Thu, 2015-05-07 at 11:01 +0000, Kumar, Venkataramanan wrote: > Hi Segher, > > Thank you I committed as r222874. > Ref: https://gcc.gnu.org/viewcvs/gcc?view=revision&revision=222874 > > Regards, > Venkat.
Venkat, This patch broke a number of MIPS tests, specifically mips32r6 tests that look for the lsa instruction (load scaled address) which shifts one register and then adds it to a second register. I am not sure if this needs to be addressed in combine.c or if we need to add a peephole optimization to mips.md to handle the new instruction sequence. What do you think? Is the change here what you would expect to see from your patch? With this C code: signed short test (signed short *a, int index) { return a[index]; } GCC/combine for mips32r6 used to produce: (insn 8 7 9 2 (set (reg/f:SI 203) (plus:SI (mult:SI (reg:SI 5 $5 [ index ]) (const_int 2 [0x2])) (reg:SI 4 $4 [ a ]))) lsa.c:3 444 {lsa} (expr_list:REG_DEAD (reg:SI 5 $5 [ index ]) (expr_list:REG_DEAD (reg:SI 4 $4 [ a ]) (nil)))) (insn 15 10 16 2 (set (reg/i:SI 2 $2) (sign_extend:SI (mem:HI (reg/f:SI 203) [1 *_5+0 S2 A16]))) lsa.c:4 237 {*extendhisi2_seh} (expr_list:REG_DEAD (reg/f:SI 203) (nil))) And would generate: lsa $4,$5,$4,1 lh $2,0($4) But now it produces: (insn 7 4 8 2 (set (reg:SI 202) (ashift:SI (reg:SI 5 $5 [ index ]) (const_int 1 [0x1]))) lsa.c:3 432 {*ashlsi3} (expr_list:REG_DEAD (reg:SI 5 $5 [ index ]) (nil))) (insn 8 7 9 2 (set (reg/f:SI 203) (plus:SI (reg:SI 4 $4 [ a ]) (reg:SI 202))) lsa.c:3 13 {*addsi3} (expr_list:REG_DEAD (reg:SI 4 $4 [ a ]) (expr_list:REG_DEAD (reg:SI 202) (nil))) (insn 15 10 16 2 (set (reg/i:SI 2 $2) (sign_extend:SI (mem:HI (reg/f:SI 203) [1 *_5+0 S2 A16]))) lsa.c:4 237 {*extendhisi2_seh} (expr_list:REG_DEAD (reg/f:SI 203) (nil))) Which generates: sll $5,$5,1 addu $4,$4,$5 lh $2,0($4) Steve Ellcey sell...@imgtec.com