Jeff Law <l...@redhat.com> writes:
> On 05/11/2015 01:46 PM, Jeff Law wrote:
> > On 05/11/2015 01:44 PM, Steve Ellcey wrote:
> >> On Mon, 2015-05-11 at 13:22 -0500, Segher Boessenkool wrote:
> >>> Hi Steve,
> >>>
> >>> On Mon, May 11, 2015 at 10:50:02AM -0700, Steve Ellcey wrote:
> >>>> This patch broke a number of MIPS tests, specifically mips32r6
> >>>> tests that look for the lsa instruction (load scaled address) which
> >>>> shifts one register and then adds it to a second register. I am
> >>>> not sure if this needs to be addressed in combine.c or if we need
> >>>> to add a peephole optimization to mips.md to handle the new
> >>>> instruction sequence.
> >>>> What do
> >>>> you think? Is the change here what you would expect to see from
> >>>> your patch?
> >>>
> >>> Yes, this is as expected. AFAICS the only change you need in the
> >>> MIPS backend is to change the "<GPR:d>lsa" pattern to match a shift
> >>> instead of a mult (and change the "const_immlsa_operand" predicate
> >>> to just match 1..4 instead of the powers).
> >>>
> >>>
> >>> Segher
> >>
> >> Hm, I thought it was going to be more complicated than that, but it
> >> seems to be working. I will do a complete test run and then submit a
> >> patch.
> > Yea, it really should be that easy.
> >
> > I'm pretty sure the sh[123]add insns in the PA need to be updated in a
> > similar manner.
> Oh, and just to be clear, I'm not expecting you to do this Steve. It'd
> be great if you did, but not required.
Does this patch effectively change the canonicalization rules? The following
Still exists in md.texi:
@item
Within address computations (i.e., inside @code{mem}), a left shift is
converted into the appropriate multiplication by a power of two.
Thanks,
Matthew
