Hi,
Please find attached the patch that fixes an ICE for prefetch.
The predicate is too lose for the constraints. Hence, the patch tightens
up the predicate to be exactly as constraint allows, avoids a “reload”
and allows better code generation.
Submitted on behalf of Andrew Pinski.
Thanks,
Naveen
2015-09-24 Andrew Pinski <apin...@cavium.com>
ChangeLog
* config/aarch64/aarch64.md (prefetch):
Change the predicate of operand 0 to register_operand.
Index: config/aarch64/aarch64.md
===================================================================
--- config/aarch64/aarch64.md (revision 228072)
+++ config/aarch64/aarch64.md (working copy)
@@ -466,7 +466,7 @@
)
(define_insn "prefetch"
- [(prefetch (match_operand:DI 0 "address_operand" "r")
+ [(prefetch (match_operand:DI 0 "register_operand" "r")
(match_operand:QI 1 "const_int_operand" "")
(match_operand:QI 2 "const_int_operand" ""))]
""
