This patch adds support for the MADDLD instruciton, which is a fused
multiply/add instruction for integers.  At this time, it is for 64-bit
multiplies only.  Eventually, we will restructure 128-bit multiply so that we
can use the 64x64 + 64 high bit varients.

I have bootstrapped a compiler with this change in and there were no
regressions.  Is it ok to apply to the trunk?

[gcc]
2015-11-10  Michael Meissner  <meiss...@linux.vnet.ibm.com>

        * config/rs6000/rs6000.h (TARGET_MADDLD): Add support for the ISA
        3.0 integer multiply-add instruction.
        * config/rs6000/rs6000.md (<u>mul<mode><dmode>3): Likewise.

[gcc/testsuite]
2015-11-10  Michael Meissner  <meiss...@linux.vnet.ibm.com>

        * gcc.target/powerpc/maddld.c: New test.


-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h  (revision 230078)
+++ gcc/config/rs6000/rs6000.h  (working copy)
@@ -571,6 +571,7 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIWUZ TARGET_POPCNTD
 #define TARGET_CTZ     TARGET_MODULO
 #define TARGET_EXTSWSLI        (TARGET_MODULO && TARGET_POWERPC64)
+#define TARGET_MADDLD  (TARGET_MODULO && TARGET_POWERPC64)
 
 #define TARGET_XSCVDPSPN       (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
 #define TARGET_XSCVSPDPN       (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 230078)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -2837,6 +2837,14 @@ (define_expand "<u>mul<mode><dmode>3"
   DONE;
 })
 
+(define_insn "*maddld4"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+       (plus:DI (mult:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+                         (match_operand:DI 2 "gpc_reg_operand" "r"))
+                (match_operand:DI 3 "gpc_reg_operand" "r")))]
+  "TARGET_MADDLD"
+  "maddld %0,%1,%2,%3"
+  [(set_attr "type" "mul")])
 
 (define_insn "udiv<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
Index: gcc/testsuite/gcc.target/powerpc/maddld.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/maddld.c   (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/maddld.c   (revision 0)
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-require-effective-target powerpc_p9modulo_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { 
"-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+long
+s_madd (long a, long b, long c)
+{
+  return (a * b) + c;
+}
+
+unsigned long
+u_madd (unsigned long a, unsigned long b, unsigned long c)
+{
+  return (a * b) + c;
+}
+
+/* { dg-final { scan-assembler-times "maddld " 2 } } */
+/* { dg-final { scan-assembler-not   "mulld "    } } */
+/* { dg-final { scan-assembler-not   "add "      } } */

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