2016-05-02 Christophe Lyon <christophe.l...@linaro.org> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New. * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New. * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New. * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New. * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New. * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New. * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.
Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737 diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c new file mode 100644 index 0000000..5f492d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrnd +#define TEST_MSG "VRND" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc new file mode 100644 index 0000000..629240d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc @@ -0,0 +1,43 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1 (NAME) + +void FNNAME (INSN) (void) +{ + /* vector_res = vrndX (vector), then store the result. */ +#define TEST_VRND2(INSN, Q, T1, T2, W, N) \ + VECT_VAR (vector_res, T1, W, N) = \ + INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N)); \ + vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N), \ + VECT_VAR (vector_res, T1, W, N)) + + /* Two auxliary macros are necessary to expand INSN. */ +#define TEST_VRND1(INSN, Q, T1, T2, W, N) \ + TEST_VRND2 (INSN, Q, T1, T2, W, N) + +#define TEST_VRND(Q, T1, T2, W, N) \ + TEST_VRND1 (INSN, Q, T1, T2, W, N) + + DECL_VARIABLE (vector, float, 32, 2); + DECL_VARIABLE (vector, float, 32, 4); + + DECL_VARIABLE (vector_res, float, 32, 2); + DECL_VARIABLE (vector_res, float, 32, 4); + + clean_results (); + + VLOAD (vector, buffer, , float, f, 32, 2); + VLOAD (vector, buffer, q, float, f, 32, 4); + + TEST_VRND ( , float, f, 32, 2); + TEST_VRND (q, float, f, 32, 4); + + CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, ""); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, ""); +} + +int +main (void) +{ + FNNAME (INSN) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c new file mode 100644 index 0000000..816fd28d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrnda +#define TEST_MSG "VRNDA" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c new file mode 100644 index 0000000..029880c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrndm +#define TEST_MSG "VRNDM" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c new file mode 100644 index 0000000..571243c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrndn +#define TEST_MSG "VRNDN" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c new file mode 100644 index 0000000..ff4771c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrndp +#define TEST_MSG "VRNDP" + +#include "vrndX.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c new file mode 100644 index 0000000..ff2357b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-add-options arm_v8_neon } */ + +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc1800000, 0xc1700000 }; +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc1800000, 0xc1700000, + 0xc1600000, 0xc1500000 }; + +#define INSN vrndx +#define TEST_MSG "VRNDX" + +#include "vrndX.inc" -- 1.9.1