Hi, Please find attached the patch that implements alu_branch fusion for AArch64. The patch doesn't change spec but improve other benchmarks.
Bootstrapped and Regression tested on aarch64-thunder-linux. Please review the patch and let us know if its okay for Stage-1? Thanks, Naveen 2017-03-06 Julian Brown <jul...@codesourcery.com> Naveen H.S <naveen.hurugalaw...@cavium.com> * config/aarch64/aarch64-fusion-pairs.def: Add ALU_BRANCH entry. * config/aarch64/aarch64.c (AARCH64_FUSE_ALU_BRANCH): New fusion type. (thunderx2t99_tunings): Set AARCH64_FUSE_ALU_BRANCH flag. (aarch_macro_fusion_pair_p): Add support for AARCH64_FUSE_ALU_BRANCH.
diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.def b/gcc/config/aarch64/aarch64-fusion-pairs.def index f0e6dbc..300cd00 100644 --- a/gcc/config/aarch64/aarch64-fusion-pairs.def +++ b/gcc/config/aarch64/aarch64-fusion-pairs.def @@ -34,5 +34,6 @@ AARCH64_FUSION_PAIR ("movk+movk", MOVK_MOVK) AARCH64_FUSION_PAIR ("adrp+ldr", ADRP_LDR) AARCH64_FUSION_PAIR ("cmp+branch", CMP_BRANCH) AARCH64_FUSION_PAIR ("aes+aesmc", AES_AESMC) +AARCH64_FUSION_PAIR ("alu+branch", ALU_BRANCH) #undef AARCH64_FUSION_PAIR diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index fa25d43..62f5461 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -792,7 +792,8 @@ static const struct tune_params thunderx2t99_tunings = &generic_approx_modes, 4, /* memmov_cost. */ 4, /* issue_rate. */ - (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC), /* fusible_ops */ + (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC + | AARCH64_FUSE_ALU_BRANCH), /* fusible_ops */ 16, /* function_align. */ 8, /* jump_align. */ 16, /* loop_align. */ @@ -14063,6 +14064,37 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) return true; } + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) + && any_uncondjump_p (curr)) + { + /* These types correspond to the reservation "vulcan_alu_basic" for + Broadcom Vulcan: these are ALU operations that produce a single uop + during instruction decoding. */ + switch (get_attr_type (prev)) + { + case TYPE_ALU_IMM: + case TYPE_ALU_SREG: + case TYPE_ADC_REG: + case TYPE_ADC_IMM: + case TYPE_ADCS_REG: + case TYPE_ADCS_IMM: + case TYPE_LOGIC_REG: + case TYPE_LOGIC_IMM: + case TYPE_CSEL: + case TYPE_ADR: + case TYPE_MOV_IMM: + case TYPE_SHIFT_REG: + case TYPE_SHIFT_IMM: + case TYPE_BFM: + case TYPE_RBIT: + case TYPE_REV: + case TYPE_EXTEND: + return true; + + default:; + } + } + return false; }