Hi Naveen,
On 15/03/17 05:32, Hurugalawadi, Naveen wrote:
Hi James,
My reason for asking is that the instruction fusion implemented in LLVM
( lib/Target/AArch64/AArch64MacroFusion.cpp::shouldScheduleAdjacent )
Sorry. There seems to be some confusion in the branch instructions.
The branch should be conditional for ALU_BRANCH fusion.
Please find attached the modified patch that fuses ALU instructions and
conditional branches.
Bootstrapped and Regression tested on aarch64-thunder-linux.
Please review the patch and let us know if its okay?
Thanks,
Naveen
+ if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH)
+ && any_condjump_p (curr))
+ {
+ /* These types correspond to the reservation "vulcan_alu_basic" for
+ Broadcom Vulcan: these are ALU operations that produce a single uop
+ during instruction decoding. */
The comment here still looks wrong. There is no vulcan_alu_basic reservation in
any of the scheduling models.
I suggest you reword the whole comment and not talk about particular CPUs, but
rather about the kinds of instructions
you want to fuse. If a reader wants to know which CPUs enable this fusion they
should be looking at the CPU tuning structures
rather than reading the comments here.
Kyrill
