tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes L1 Icache which can access L1 Dcache. Therefore, DC CVAU is not necessary in __aarch64_sync_cache_range for tsv110, is there any good idea to skip DC CVAU operation for tsv110.
Any thoughts and ideas are welcome. Shaokun Zhang (1): [aarch64] Add HiSilicon tsv110 CPU support. gcc/ChangeLog | 9 +++ gcc/config/aarch64/aarch64-cores.def | 5 ++ gcc/config/aarch64/aarch64-cost-tables.h | 103 +++++++++++++++++++++++++++++++ gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/aarch64/aarch64.c | 79 ++++++++++++++++++++++++ gcc/doc/invoke.texi | 2 +- 6 files changed, 198 insertions(+), 2 deletions(-) -- 2.7.4
