On 23/05/2018 03:50, Zhangshaokun wrote:
Hi Ramana,
On 2018/5/22 18:28, Ramana Radhakrishnan wrote:
On Tue, May 22, 2018 at 9:40 AM, Shaokun Zhang
<zhangshao...@hisilicon.com> wrote:
tsv110 is designed by HiSilicon and supports v8_4A, it also optimizes
L1 Icache which can access L1 Dcache.
Therefore, DC CVAU is not necessary in __aarch64_sync_cache_range for
tsv110, is there any good idea to skip DC CVAU operation for tsv110.
A solution would be to use an ifunc but on a cpu variant.
ifunc, can you give further explanation?
If on a cpu variant, for HiSilicon tsv110, we have two version and CPU variants
are 0 and 1. Both are expected to skip DC CVAU operation in sync icache and
dcache.
Since it is not necessary for sync icache and dcache, it is beneficial for
performance to skip the redundant DC CVAU and do IC IVAU only.
For JVM, __clear_cache is called many times.
Thanks for some more detail as to where you think you want to use this.
Have you investigated whether the jvm can actually elide such a call
rather than trying to fix this in the toolchain ?
If you really need to think about solutions in the toolchain -
The simplest first step would be to implement the changes hinted at by
the comment in aarch64.h .
If you read the comment above CLEAR_INSN_CACHE in aarch64.h you would
see that
/* This definition should be relocated to aarch64-elf-raw.h. This macro
should be undefined in aarch64-linux.h and a clear_cache pattern
implmented to emit either the call to __aarch64_sync_cache_range()
directly or preferably the appropriate sycall or cache clear
instructions inline. */
#define CLEAR_INSN_CACHE(beg, end) \
extern void __aarch64_sync_cache_range (void *, void *); \
__aarch64_sync_cache_range (beg, end)
Thus I would expect that by implementing the clear_cache pattern and
deciding whether to put out the call to the __aarch64_sync_cache_range
function or not depending on whether you had the tsv110 chosen on the
command line would allow you to have an idea of what the performance
gain actually is by compiling the jvm with -mcpu=tsv110 vs
-march=armv8-a. You probably also want to clean up the trampoline_init
code while you are here.
I do think that's something that should be easy enough to do and the
subject of a patch series in its own right. If your users can rebuild
the world for tsv110 then this is sufficient.
If you want to have a single jvm binary without any run time checks,
then you need to investigate the use of ifuncs which are a mechanism in
the GNU toolchain for some of this kind of stuff. We tend not to ifuncs
on a per CPU basis unless there is a very good reason and the
performance improvement is worth it (but probably more on a per
architecture or per architectural basis) and you will need to make the
case for it including what sort of performance benefits it gives. Some
introduction about this feature can be found here.
https://sourceware.org/glibc/wiki/GNU_IFUNC
regards
Ramana
Hi ARM guys,
are you happy to share yours idea about this?
Is this really that important for performance and on what workloads ?
Since it is not necessary for sync icache and dcache, it is beneficial for
performance to skip the redundant DC CVAU and do IC IVAU only.
For JVM, __clear_cache is called many times.
Thanks,
Shaokun
regards
Ramana
Any thoughts and ideas are welcome.
Shaokun Zhang (1):
[aarch64] Add HiSilicon tsv110 CPU support.
gcc/ChangeLog | 9 +++
gcc/config/aarch64/aarch64-cores.def | 5 ++
gcc/config/aarch64/aarch64-cost-tables.h | 103 +++++++++++++++++++++++++++++++
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/config/aarch64/aarch64.c | 79 ++++++++++++++++++++++++
gcc/doc/invoke.texi | 2 +-
6 files changed, 198 insertions(+), 2 deletions(-)
--
2.7.4
