On 9/27/18 6:04 AM, Matthew Malcomson wrote: > Hi Richard, > > > On 26/09/18 06:03, rth7...@gmail.com wrote: >> From: Richard Henderson <richard.hender...@linaro.org> >> >> This pattern will only be used with the __sync functions, because >> we do not yet have a bare TImode atomic load. >> >> > I don't have any comment on the overall aim of the patch series, but in > this particular > patch it looks like you doesn't ensure the register pairs for casp are > even-odd. > > This is the restriction in the Arm Arm decode for casp variants as > if Rs<0> == '1' then UnallocatedEncoding(); > if Rt<0> == '1' then UnallocatedEncoding();
Oops. I missed this bit when reading the docs. Thanks. I'll incorporate your even register class patch into the next round. r~
