On 27/09/18 17:32, Richard Henderson wrote:
On 9/27/18 6:04 AM, Matthew Malcomson wrote:
Hi Richard,
On 26/09/18 06:03, rth7...@gmail.com wrote:
From: Richard Henderson <richard.hender...@linaro.org>
This pattern will only be used with the __sync functions, because
we do not yet have a bare TImode atomic load.
I don't have any comment on the overall aim of the patch series, but in
this particular
patch it looks like you doesn't ensure the register pairs for casp are
even-odd.
This is the restriction in the Arm Arm decode for casp variants as
if Rs<0> == '1' then UnallocatedEncoding();
if Rt<0> == '1' then UnallocatedEncoding();
Oops. I missed this bit when reading the docs. Thanks.
I'll incorporate your even register class patch into the next round.
r~
Just a heads up on that register class patch (because it's use is not
very intuitive):
To allow any valid register pair combination between operands you need
to have all combinations of the two constraints in your patterns
alternatives.
So e.g. the "out" operand might have constraints like "Uep,Uex,Uep,Uex"
while the "desired" operand would have "Uep,Uep,Uex,Uex".
[It's ugly, but the best of the options I found ].
M
