On Tue, Nov 13, 2018 at 05:17:41AM -0600, Segher Boessenkool wrote:
> On Tue, Nov 13, 2018 at 12:02:55PM +1030, Alan Modra wrote:
> > OK, fair enough.  Another option is to just disable -many when gcc is
> > in development, like we enable checking.
> 
> That is a good plan for GCC 9 at least.

Here's the patch.  Bootstrapped etc. powerpc64le-linux with resultant
fail of clone2 test as already noted.  On top of
https://gcc.gnu.org/ml/gcc-patches/2018-11/msg00924.html so needs
to be hand edited if applying without that patch.  I'm going to be
away for a few days without email access, which means I probably won't
be seeing any replies until Monday.

        * config/rs6000/rs6000.h (ASM_OPT_ANY): Define.
        (ASM_CPU_SPEC): Conditionally add -many.
        * config/rs6000/aix61.h (ASM_CPU_SPEC): Likewise.
        * config/rs6000/aix71.h (ASM_CPU_SPEC): Likewise.
        * testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c: Don't use
        power mnemonics.

diff --git a/gcc/config/rs6000/aix61.h b/gcc/config/rs6000/aix61.h
index 353e5d6cfeb..809c5d8d599 100644
--- a/gcc/config/rs6000/aix61.h
+++ b/gcc/config/rs6000/aix61.h
@@ -91,8 +91,8 @@ do {                                                          
        \
 %{mcpu=630: -m620} \
 %{mcpu=970: -m970} \
 %{mcpu=G5: -m970} \
-%{mvsx: %{!mcpu*: -mpwr6}} \
--many"
+%{mvsx: %{!mcpu*: -mpwr6}}" \
+ASM_OPT_ANY
 
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpwr4"
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 2398ed64baa..319bd2dc013 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -89,8 +89,8 @@ do {                                                          
        \
            maltivec: -m970; \
            maix64|mpowerpc64: -mppc64; \
            : %(asm_default)}; \
-  :%eMissing -mcpu option in ASM_SPEC_CPU?\n} \
--many"
+  :%eMissing -mcpu option in ASM_SPEC_CPU?\n}" \
+ASM_OPT_ANY
 
 #undef ASM_DEFAULT_SPEC
 #define ASM_DEFAULT_SPEC "-mpwr4"
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index d75137cf8f5..613d16add69 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -72,6 +72,12 @@
 #define PPC405_ERRATUM77 0
 #endif
 
+#if CHECKING_P
+#define ASM_OPT_ANY ""
+#else
+#define ASM_OPT_ANY " -many"
+#endif
+
 /* Common ASM definitions used by ASM_SPEC among the various targets for
    handling -mcpu=xxx switches.  There is a parallel list in driver-rs6000.c to
    provide the default assembler options if the user uses -mcpu=native, so if
@@ -137,8 +143,8 @@
            mvsx: -mpower7; \
            mpowerpc64: -mppc64;: %(asm_default)}; \
   :%eMissing -mcpu option in ASM_SPEC_CPU?\n} \
-%{mvsx: -mvsx -maltivec; maltivec: -maltivec} \
--many"
+%{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \
+ASM_OPT_ANY
 
 #define CPP_DEFAULT_SPEC ""
 
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c 
b/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
index 14908dba690..eea7f6ffc2e 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
@@ -45,14 +45,14 @@ __asm__ ("\t.globl\t" #NAME "_asm\n\t"                      
                \
         #NAME "_asm:\n\t"                                              \
         "lis 11,gparms@ha\n\t"                                         \
         "la 11,gparms@l(11)\n\t"                                       \
-        "st 3,0(11)\n\t"                                               \
-        "st 4,4(11)\n\t"                                               \
-        "st 5,8(11)\n\t"                                               \
-        "st 6,12(11)\n\t"                                              \
-        "st 7,16(11)\n\t"                                              \
-        "st 8,20(11)\n\t"                                              \
-        "st 9,24(11)\n\t"                                              \
-        "st 10,28(11)\n\t"                                             \
+        "stw 3,0(11)\n\t"                                              \
+        "stw 4,4(11)\n\t"                                              \
+        "stw 5,8(11)\n\t"                                              \
+        "stw 6,12(11)\n\t"                                             \
+        "stw 7,16(11)\n\t"                                             \
+        "stw 8,20(11)\n\t"                                             \
+        "stw 9,24(11)\n\t"                                             \
+        "stw 10,28(11)\n\t"                                            \
         "stfd 1,32(11)\n\t"                                            \
         "stfd 2,40(11)\n\t"                                            \
         "stfd 3,48(11)\n\t"                                            \

-- 
Alan Modra
Australia Development Lab, IBM

Reply via email to