This patch enables MVE vorrq instructions for auto-vectorization. MVE vorrq insns in mve.md are modified to use ior instead of unspec expression to support ior<mode>3. The ior<mode>3 expander is added to vec-common.md
2020-11-13 Christophe Lyon <christophe.l...@linaro.org> gcc/ * config/arm/iterators.md (supf): Remove VORRQ_S and VORRQ_U. (VORRQ): Remove. * config/arm/mve.md (mve_vorrq_s<mode>): New entry for vorr instruction using expression ior. (mve_vorrq_u<mode>): New expander. * config/arm/neon.md (ior<mode>3): Renamed into ior<mode>3_neon. * config/arm/unspecs.md (VORRQ_S, VORRQ_U): Remove. * config/arm/vec-common.md (ior<mode>3): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-vorr.c: Add vorr tests. --- gcc/config/arm/iterators.md | 5 ++-- gcc/config/arm/mve.md | 17 ++++++++++---- gcc/config/arm/neon.md | 2 +- gcc/config/arm/unspecs.md | 2 -- gcc/config/arm/vec-common.md | 15 ++++++++++++ gcc/testsuite/gcc.target/arm/simd/mve-vorr.c | 34 ++++++++++++++++++++++++++++ 6 files changed, 64 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vorr.c diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 72039e4..5fcb7af 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1247,8 +1247,8 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VMULLBQ_INT_S "s") (VMULLBQ_INT_U "u") (VQADDQ_S "s") (VMULLTQ_INT_S "s") (VMULLTQ_INT_U "u") (VQADDQ_U "u") (VMULQ_N_S "s") (VMULQ_N_U "u") (VMULQ_S "s") - (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") (VORRQ_S "s") - (VORRQ_U "u") (VQADDQ_N_S "s") (VQADDQ_N_U "u") + (VMULQ_U "u") (VORNQ_S "s") (VORNQ_U "u") + (VQADDQ_N_S "s") (VQADDQ_N_U "u") (VQRSHLQ_N_S "s") (VQRSHLQ_N_U "u") (VQRSHLQ_S "s") (VQRSHLQ_U "u") (VQSHLQ_N_S "s") (VQSHLQ_N_U "u") (VQSHLQ_R_S "s") (VQSHLQ_R_U "u") (VQSHLQ_S "s") @@ -1523,7 +1523,6 @@ (define_int_iterator VMULLTQ_INT [VMULLTQ_INT_U VMULLTQ_INT_S]) (define_int_iterator VMULQ [VMULQ_U VMULQ_S]) (define_int_iterator VMULQ_N [VMULQ_N_U VMULQ_N_S]) (define_int_iterator VORNQ [VORNQ_U VORNQ_S]) -(define_int_iterator VORRQ [VORRQ_S VORRQ_U]) (define_int_iterator VQADDQ [VQADDQ_U VQADDQ_S]) (define_int_iterator VQADDQ_N [VQADDQ_N_S VQADDQ_N_U]) (define_int_iterator VQRSHLQ [VQRSHLQ_S VQRSHLQ_U]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 975eb7d..0f04044 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1610,17 +1610,24 @@ (define_insn "mve_vornq_<supf><mode>" ;; ;; [vorrq_s, vorrq_u]) ;; -(define_insn "mve_vorrq_<supf><mode>" +(define_insn "mve_vorrq_s<mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:MVE_2 2 "s_register_operand" "w")] - VORRQ)) + (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w") + (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vorr %q0, %q1, %q2" + "vorr\t%q0, %q1, %q2" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vorrq_u<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand") + (match_operand:MVE_2 2 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vqaddq_n_s, vqaddq_n_u]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index dc4707d..669c34d 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -690,7 +690,7 @@ (define_insn "neon_vcvt<NEON_VCVT:nvrint_variant><su_optab><VCVTF:mode><v_cmp_re (set_attr "predicable" "no")] ) -(define_insn "ior<mode>3" +(define_insn "ior<mode>3_neon" [(set (match_operand:VDQ 0 "s_register_operand" "=w,w") (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0") (match_operand:VDQ 2 "neon_logic_op2" "w,Dl")))] diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index e8bf68e..f111ad8 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -624,7 +624,6 @@ (define_c_enum "unspec" [ VMULQ_S VMULQ_N_S VORNQ_S - VORRQ_S VQADDQ_S VQADDQ_N_S VQRSHLQ_S @@ -670,7 +669,6 @@ (define_c_enum "unspec" [ VMULQ_U VMULQ_N_U VORNQ_U - VORRQ_U VQADDQ_U VQADDQ_N_U VQRSHLQ_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 3dd694c..413fb07 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -187,3 +187,18 @@ (define_expand "and<mode>3" (match_operand:VNINOTM1 2 "neon_inv_logic_op2" "")))] "TARGET_NEON" ) + +(define_expand "ior<mode>3" + [(set (match_operand:VNIM1 0 "s_register_operand" "") + (ior:VNIM1 (match_operand:VNIM1 1 "s_register_operand" "") + (match_operand:VNIM1 2 "neon_logic_op2" "")))] + "TARGET_NEON + || (TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))" +) + +(define_expand "ior<mode>3" + [(set (match_operand:VNINOTM1 0 "s_register_operand" "") + (ior:VNINOTM1 (match_operand:VNINOTM1 1 "s_register_operand" "") + (match_operand:VNINOTM1 2 "neon_logic_op2" "")))] + "TARGET_NEON" +) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vorr.c b/gcc/testsuite/gcc.target/arm/simd/mve-vorr.c new file mode 100644 index 0000000..c7b59bb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vorr.c @@ -0,0 +1,34 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include <stdint.h> + +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \ + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \ + int i; \ + for (i=0; i<NB; i++) { \ + dest[i] = a[i] OP b[i]; \ + } \ +} + +/* 64-bit vectors. */ +FUNC(s, int, 32, 2, |, vorr) +FUNC(u, uint, 32, 2, |, vorr) +FUNC(s, int, 16, 4, |, vorr) +FUNC(u, uint, 16, 4, |, vorr) +FUNC(s, int, 8, 8, |, vorr) +FUNC(u, uint, 8, 8, |, vorr) + +/* 128-bit vectors. */ +FUNC(s, int, 32, 4, |, vorr) +FUNC(u, uint, 32, 4, |, vorr) +FUNC(s, int, 16, 8, |, vorr) +FUNC(u, uint, 16, 8, |, vorr) +FUNC(s, int, 8, 16, |, vorr) +FUNC(u, uint, 8, 16, |, vorr) + +/* MVE has only 128-bit vectors, so we can vectorize only half of the + functions above. */ +/* { dg-final { scan-assembler-times {vorr\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */ -- 2.7.4