This patch enables MVE vmvnq instructions for auto-vectorization. MVE vmvnq insns in mve.md are modified to use 'not' instead of unspec expression to support one_cmpl<mode>2. The one_cmpl<mode>2 expander is added to vec-common.md.
2020-11-12 Christophe Lyon <christophe.l...@linaro.org> gcc/ * config/arm/iterators.md (VDQNOTM5): New mode iterator. (supf): Remove VMVNQ_S and VMVNQ_U. (VMVNQ): Remove. * config/arm/mve.md (mve_vmvnq_u<mode>): New entry for vmvn instruction using expression not. (mve_vmvnq_s<mode>): New expander. * config/arm/neon.md (one_cmpl<mode>2): Renamed into one_cmpl<mode>2_insn. * config/arm/unspscs.md (VMVNQ_S, VMVNQ_U): Remove. * config/arm/vec-common.md (one_cmpl<mode>2): New expander. gcc/testsuite/ * gcc.target/arm/simd/mve-vmvn.c: Add tests for vmvn. --- gcc/config/arm/iterators.md | 6 ++++-- gcc/config/arm/mve.md | 14 +++++++++---- gcc/config/arm/neon.md | 4 ++-- gcc/config/arm/unspecs.md | 2 -- gcc/config/arm/vec-common.md | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c | 31 ++++++++++++++++++++++++++++ 6 files changed, 59 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 0195275..75af7aa 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -72,6 +72,9 @@ (define_mode_iterator VNIM1 [V16QI V8HI V4SI V4SF V2DI]) ;; Integer and float modes supported by Neon and IWMMXT but not MVE. (define_mode_iterator VNINOTM1 [V2SI V4HI V8QI V2SF]) +;; Integer modes supported by Neon but not part of MVE_5 +(define_mode_iterator VDQNOTM5 [V8QI V16QI V4HI V2SI V2DI]) + ;; Integer and float modes supported by Neon and IWMMXT, except V2DI. (define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) @@ -1216,7 +1219,7 @@ (define_int_attr mmla_sfx [(UNSPEC_MATMUL_S "s8") (UNSPEC_MATMUL_U "u8") (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s") - (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u") + (VREV64Q_U "u") (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s") (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u") (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s") @@ -1476,7 +1479,6 @@ (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) (define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S]) (define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S]) -(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S]) (define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S]) (define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S]) (define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 55b2991..1d18de5 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -433,16 +433,22 @@ (define_insn "mve_vnegq_s<mode>" ;; ;; [vmvnq_u, vmvnq_s]) ;; -(define_insn "mve_vmvnq_<supf><mode>" +(define_insn "mve_vmvnq_u<mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] - VMVNQ)) + (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vmvn %q0, %q1" + "vmvn\t%q0, %q1" [(set_attr "type" "mve_move") ]) +(define_expand "mve_vmvnq_s<mode>" + [ + (set (match_operand:MVE_2 0 "s_register_operand") + (not:MVE_2 (match_operand:MVE_2 1 "s_register_operand"))) + ] + "TARGET_HAVE_MVE" +) ;; ;; [vdupq_n_u, vdupq_n_s]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 5090673..ae70fa8 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -756,7 +756,7 @@ (define_insn "xor<mode>3_neon" [(set_attr "type" "neon_logic<q>")] ) -(define_insn "one_cmpl<mode>2" +(define_insn "one_cmpl<mode>2_insn" [(set (match_operand:VDQ 0 "s_register_operand" "=w") (not:VDQ (match_operand:VDQ 1 "s_register_operand" "w")))] "TARGET_NEON" @@ -3206,7 +3206,7 @@ (define_expand "neon_vmvn<mode>" (match_operand:VDQIW 1 "s_register_operand")] "TARGET_NEON" { - emit_insn (gen_one_cmpl<mode>2 (operands[0], operands[1])); + emit_insn (gen_one_cmpl<mode>2_insn (operands[0], operands[1])); DONE; }) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 78313ea..a2866c1 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -550,8 +550,6 @@ (define_c_enum "unspec" [ VREV64Q_U VQABSQ_S VNEGQ_S - VMVNQ_S - VMVNQ_U VDUPQ_N_U VDUPQ_N_S VCLZQ_U diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 915dcb0..5c6e847 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -262,3 +262,15 @@ (define_expand "vlshr<mode>3" DONE; } }) + +(define_expand "one_cmpl<mode>2" + [(set (match_operand:MVE_5 0 "s_register_operand") + (not:MVE_5 (match_operand:MVE_5 1 "s_register_operand")))] + "TARGET_NEON || TARGET_HAVE_MVE" +) + +(define_expand "one_cmpl<mode>2" + [(set (match_operand:VDQNOTM5 0 "s_register_operand") + (not:VDQNOTM5 (match_operand:VDQNOTM5 1 "s_register_operand")))] + "TARGET_NEON" +) diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c b/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c new file mode 100644 index 0000000..612c179 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/mve-vmvn.c @@ -0,0 +1,31 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include <stdint.h> + +#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \ + void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \ + int i; \ + for (i=0; i<NB; i++) { \ + dest[i] = OP a[i]; \ + } \ +} + +/* vmnvq supports only 16-bit and 32-bit elements. */ +/* 64-bit vectors. */ +FUNC(s, int, 32, 2, ~, vmvn) +FUNC(u, uint, 32, 2, ~, vmvn) +FUNC(s, int, 16, 4, ~, vmvn) +FUNC(u, uint, 16, 4, ~, vmvn) + +/* 128-bit vectors. */ +FUNC(s, int, 32, 4, ~, vmvn) +FUNC(u, uint, 32, 4, ~, vmvn) +FUNC(s, int, 16, 8, ~, vmvn) +FUNC(u, uint, 16, 8, ~, vmvn) + +/* MVE has only 128-bit vectors, so we can vectorize only half of the + functions above. */ +/* { dg-final { scan-assembler-times {vmvn\tq[0-9]+, q[0-9]+} 4 } } */ -- 2.7.4