On Fri, Mar 12, 2021 at 06:05:34PM +0100, Uros Bizjak wrote:
> Untested patch that introduces YW to some remaining pextr
> instructions, fixes one case of 128bit vpsrldq and 128bit vpalignr w/o
> AVX512VL.
Not sure I can find the vpsrldq change in there.
> @@ -21599,11 +21590,11 @@
> (set_attr "mode" "<sseinsnmode>")])
>
> (define_insn "*ssse3_palignr<mode>_perm"
> - [(set (match_operand:V_128 0 "register_operand" "=x,x,v")
> + [(set (match_operand:V_128 0 "register_operand" "=x,Yw")
> (vec_select:V_128
> - (match_operand:V_128 1 "register_operand" "0,x,v")
> + (match_operand:V_128 1 "register_operand" "0,Yw")
> (match_parallel 2 "palignr_operand"
> - [(match_operand 3 "const_int_operand" "n,n,n")])))]
> + [(match_operand 3 "const_int_operand" "n,n")])))]
> "TARGET_SSSE3"
and I believe I had exactly this change in an earlier version of my patch
and it didn't work (broke
+FAIL: gcc.target/i386/avx512vl-vpalignr-4.c scan-assembler-not
vpalignr[^\\n\\r]*\\\\\$8[^\\n\\r]*%xmm16[^\\n\\r]*%xmm16[^\\n\\r]*%xmm16
), which is why I've reverted it.
It could use YW instead of Yw though and then it should work.
> {
> operands[2] = (GEN_INT (INTVAL (operands[3])
> @@ -21614,19 +21605,18 @@
> case 0:
> return "palignr\t{%2, %1, %0|%0, %1, %2}";
> case 1:
> - case 2:
> return "vpalignr\t{%2, %1, %1, %0|%0, %1, %1, %2}";
> default:
> gcc_unreachable ();
> }
> }
> - [(set_attr "isa" "noavx,avx,avx512bw")
> + [(set_attr "isa" "noavx,avx")
> (set_attr "type" "sseishft")
> (set_attr "atom_unit" "sishuf")
> - (set_attr "prefix_data16" "1,*,*")
> + (set_attr "prefix_data16" "1,*")
> (set_attr "prefix_extra" "1")
> (set_attr "length_immediate" "1")
> - (set_attr "prefix" "orig,vex,evex")])
> + (set_attr "prefix" "orig,maybe_evex")])
>
> (define_expand "avx512vl_vinsert<mode>"
> [(match_operand:VI48F_256 0 "register_operand")
Jakub
