On Fri, Mar 12, 2021 at 6:32 PM Jakub Jelinek <ja...@redhat.com> wrote:
>
> On Fri, Mar 12, 2021 at 06:05:34PM +0100, Uros Bizjak wrote:
> > Untested patch that introduces YW to some remaining pextr
> > instructions, fixes one case of 128bit vpsrldq and 128bit vpalignr w/o
> > AVX512VL.
>
> Not sure I can find the vpsrldq change in there.
It is hidden in *vec_extractv4si pattern:
(define_insn "*vec_extractv4si"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,Yr,*x,x,Yv")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,Yr,*x,Yw")
(vec_select:SI
- (match_operand:V4SI 1 "register_operand" "x,v,0,0,x,v")
+ (match_operand:V4SI 1 "register_operand" " x, v, 0, 0,Yw")
(parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
"TARGET_SSE4_1"
{
@@ -15668,7 +15660,6 @@
return "psrldq\t{%2, %0|%0, %2}";
case 4:
- case 5:
operands[2] = GEN_INT (INTVAL (operands[2]) * 4);
return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
>
> > @@ -21599,11 +21590,11 @@
> > (set_attr "mode" "<sseinsnmode>")])
> >
> > (define_insn "*ssse3_palignr<mode>_perm"
> > - [(set (match_operand:V_128 0 "register_operand" "=x,x,v")
> > + [(set (match_operand:V_128 0 "register_operand" "=x,Yw")
> > (vec_select:V_128
> > - (match_operand:V_128 1 "register_operand" "0,x,v")
> > + (match_operand:V_128 1 "register_operand" "0,Yw")
> > (match_parallel 2 "palignr_operand"
> > - [(match_operand 3 "const_int_operand" "n,n,n")])))]
> > + [(match_operand 3 "const_int_operand" "n,n")])))]
> > "TARGET_SSSE3"
>
> and I believe I had exactly this change in an earlier version of my patch
> and it didn't work (broke
> +FAIL: gcc.target/i386/avx512vl-vpalignr-4.c scan-assembler-not
> vpalignr[^\\n\\r]*\\\\\$8[^\\n\\r]*%xmm16[^\\n\\r]*%xmm16[^\\n\\r]*%xmm16
> ), which is why I've reverted it.
> It could use YW instead of Yw though and then it should work.
My copy of x86 ISA says that vpalignr with xmm operands needs AVX512VL
and AVX512BW. Is the testcase correct?
[uros@localhost test]$ cat palignr.s
vpalignr $2, %xmm22, %xmm23, %xmm24
[uros@localhost test]$ as -march=+noavx512vl palignr.s
palignr.s: Assembler messages:
palignr.s:1: Error: unsupported instruction `vpalignr'
[uros@localhost test]$ as -march=+noavx512bw palignr.s
palignr.s: Assembler messages:
palignr.s:1: Error: unsupported instruction `vpalignr'
[uros@localhost test]$ cat palignr.s
vpalignr $2, %xmm2, %xmm3, %xmm4
[uros@localhost test]$ as -march=+noavx512vl+noavx512bw palignr.s
Uros.
