> -----Original Message-----
> From: Richard Sandiford <[email protected]>
> Sent: 14 December 2021 11:58
> To: Przemyslaw Wirkus <[email protected]>
> Cc: [email protected]; Richard Earnshaw
> <[email protected]>; Marcus Shawcroft
> <[email protected]>; Kyrylo Tkachov <[email protected]>
> Subject: Re: [PATCH][GCC] aarch64: Add LS64 extension and intrinsics
>
> Przemyslaw Wirkus <[email protected]> writes:
> > Hello Richard,
> >
> > I've updated my patch following all your comments. Thank you.
> >
> > Boostrapped on aarch64-linux-gnu and all new ACLE tests pass.
> >
> > OK to install?
>
> Thanks. OK with a couple of formatting nits:
Updated and committed:
commit fdcddba8f29ea3878851b8b4cd37d0fd3476d3bf
Thank you!
> > @@ -2130,6 +2203,57 @@ aarch64_expand_builtin_tme (int fcode, tree
> exp, rtx target)
> > return target;
> > }
> >
> > +/* Function to expand an expression EXP which calls one of the
> Load/Store
> > + 64 Byte extension (LS64) builtins FCODE with the result going to
> > +TARGET. */ static rtx
> > +aarch64_expand_builtin_ls64 (int fcode, tree exp, rtx target) {
> > + expand_operand ops[3];
> > +
> > + switch (fcode)
> > + {
> > + case AARCH64_LS64_BUILTIN_LD64B:
> > + {
> > + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
> > + create_output_operand (&ops[0], target, V8DImode);
> > + create_input_operand (&ops[1], op0, DImode);
> > + expand_insn (CODE_FOR_ld64b, 2, ops);
> > + return ops[0].value;
> > + }
> > + case AARCH64_LS64_BUILTIN_ST64B:
> > + {
> > + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
> > + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
> > + create_output_operand (&ops[0], op0, DImode);
> > + create_input_operand (&ops[1], op1, V8DImode);
> > + expand_insn (CODE_FOR_st64b, 2, ops);
> > + return const0_rtx;
> > + }
> > + case AARCH64_LS64_BUILTIN_ST64BV:
> > + {
> > + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
> > + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
> > + create_output_operand (&ops[0], target, DImode);
> > + create_input_operand (&ops[1], op0, DImode);
> > + create_input_operand (&ops[2], op1, V8DImode);
> > + expand_insn (CODE_FOR_st64bv, 3, ops);
> > + return ops[0].value;
> > + }
> > + case AARCH64_LS64_BUILTIN_ST64BV0:
> > + {
> > + rtx op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
> > + rtx op1 = expand_normal (CALL_EXPR_ARG (exp, 1));
> > + create_output_operand (&ops[0], target, DImode);
> > + create_input_operand (&ops[1], op0, DImode);
> > + create_input_operand (&ops[2], op1, V8DImode);
> > + expand_insn (CODE_FOR_st64bv0, 3, ops);
> > + return ops[0].value;
> > + }
> > + }
> > +
> > + gcc_unreachable ();
>
> This line should be indented by 2 spaces rather than 4.
>
> > +}
> > +
> > /* Expand a random number builtin EXP with code FCODE, putting the
> result
> > int TARGET. If IGNORE is true the return value is ignored. */
> >
> > […]
> > diff --git a/gcc/config/aarch64/aarch64.c
> > b/gcc/config/aarch64/aarch64.c index
> >
> be24b7320d28deed9a19a0451c96bd67d2fb3104..e0ceba68968a28a9fcf1ba6
> e3a30
> > 36783b0931b0 100644
> > --- a/gcc/config/aarch64/aarch64.c
> > +++ b/gcc/config/aarch64/aarch64.c
> > @@ -10013,8 +10013,12 @@ aarch64_classify_address (struct
> aarch64_address_info *info,
> > instruction memory accesses. */
> > if (mode == TImode || mode == TFmode)
> > return (aarch64_offset_7bit_signed_scaled_p (DImode, offset)
> > - && (aarch64_offset_9bit_signed_unscaled_p (mode, offset)
> > - || offset_12bit_unsigned_scaled_p (mode, offset)));
> > + && (aarch64_offset_9bit_signed_unscaled_p (mode, offset)
> > + || offset_12bit_unsigned_scaled_p (mode, offset)));
>
> The original formatting was correct here.
>
> > +
> > + if (mode == V8DImode)
> > + return (aarch64_offset_7bit_signed_scaled_p (DImode, offset)
> > + && aarch64_offset_7bit_signed_scaled_p (DImode, offset +
> > +48));
> >
> > /* A 7bit offset check because OImode will emit a ldp/stp
> > instruction (only big endian will get here).
