> -----Original Message----- > From: Andrea Corallo <andrea.cora...@arm.com> > Sent: Thursday, November 17, 2022 4:38 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com>; Richard Earnshaw > <richard.earns...@arm.com>; Andrea Corallo <andrea.cora...@arm.com> > Subject: [PATCH 19/35] arm: improve tests and fix vsubq* > > gcc/ChangeLog: > > * config/arm/mve.md (mve_vsubq_n_f<mode>): Fix spacing. > > gcc/testsuite/ChangeLog: > > * gcc.target/arm/mve/intrinsics/vsubq_f16.c: Improve test. > * gcc.target/arm/mve/intrinsics/vsubq_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_n_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise. Ok. Thanks, Kyrill > --- > gcc/config/arm/mve.md | 2 +- > .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 16 ++++++- > .../arm/mve/intrinsics/vsubq_m_f16.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_f32.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_f16.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_f32.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_s16.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_s32.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_s8.c | 26 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_u16.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_u32.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_n_u8.c | 42 ++++++++++++++-- > .../arm/mve/intrinsics/vsubq_m_s16.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_s32.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_s8.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_u16.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_u32.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_m_u8.c | 25 ++++++++-- > .../arm/mve/intrinsics/vsubq_n_f16.c | 28 ++++++++++- > .../arm/mve/intrinsics/vsubq_n_f32.c | 28 ++++++++++- > .../arm/mve/intrinsics/vsubq_n_s16.c | 17 +++++-- > .../arm/mve/intrinsics/vsubq_n_s32.c | 17 +++++-- > .../arm/mve/intrinsics/vsubq_n_s8.c | 17 +++++-- > .../arm/mve/intrinsics/vsubq_n_u16.c | 29 +++++++++-- > .../arm/mve/intrinsics/vsubq_n_u32.c | 29 +++++++++-- > .../arm/mve/intrinsics/vsubq_n_u8.c | 29 +++++++++-- > .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 16 ++++++- > .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 16 ++++++- > .../arm/mve/intrinsics/vsubq_x_f16.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_f32.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_f16.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_f32.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_s16.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_s32.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_s8.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_u16.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_u32.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_n_u8.c | 48 +++++++++++++++++-- > .../arm/mve/intrinsics/vsubq_x_s16.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_s32.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_s8.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_u16.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_u32.c | 32 +++++++++++-- > .../arm/mve/intrinsics/vsubq_x_u8.c | 32 +++++++++++-- > 49 files changed, 1261 insertions(+), 145 deletions(-) > > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 5ce2a289225..714dc6fc7ce 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -679,7 +679,7 @@ (define_insn "mve_vsubq_n_f<mode>" > VSUBQ_N_F)) > ] > "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" > - "vsub.f<V_sz_elem> %q0, %q1, %2" > + "vsub.f<V_sz_elem>\t%q0, %q1, %2" > [(set_attr "type" "mve_move") > ]) > > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c > index 8e3ce24fa49..3d82b081ca2 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b) > { > return vsubq_f16 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.f16" } } */ > > +/* > +**foo1: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16x8_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.f16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c > index 5cb239d70fa..d0f64bb9872 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b) > { > return vsubq_f32 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.f32" } } */ > > +/* > +**foo1: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32x4_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.f32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c > index f4b3f806822..434b0a7ced8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vsubq_m_f16 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c > index 75dbf9335c9..0b8e056647e 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vsubq_m_f32 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c > index 556a0845087..abbd60060a7 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) > { > return vsubq_m_n_f16 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t inactive, float16x8_t a, float16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo2 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1.1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c > index e53f5f1966a..40ca4284a1f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) > { > return vsubq_m_n_f32 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t inactive, float32x4_t a, float32_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo2 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1.1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c > index 73443d500ba..f13eff8ad2d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) > { > return vsubq_m_n_s16 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, int16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c > index b4031111678..21ba17ba869 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) > { > return vsubq_m_n_s32 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, int32_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c > index 5c4e1019225..c75b8b5420d 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c > @@ -1,23 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) > { > return vsubq_m_n_s8 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, int8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c > index 04a3036ede8..700bc01833c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) > { > return vsubq_m_n_u16 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t inactive, uint16x8_t a, uint16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t inactive, uint16x8_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c > index a21f9366373..25dd37ae5b2 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) > { > return vsubq_m_n_u32 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t inactive, uint32x4_t a, uint32_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t inactive, uint32x4_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c > index 18f635f1e1a..4fed154d258 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c > @@ -1,23 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) > { > return vsubq_m_n_u8 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t inactive, uint8x16_t a, uint8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t inactive, uint8x16_t a, mve_pred16_t p) > +{ > + return vsubq_m (inactive, a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c > index 598d648887b..dde77dc51b7 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vsubq_m_s16 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c > index af6750278f1..8770e31ad95 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vsubq_m_s32 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c > index 5effbe2e017..c9813313594 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vsubq_m_s8 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c > index 12218ae6791..eebc3ad6929 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vsubq_m_u16 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c > index 3a63eeb2b3d..d85bbec7ebf 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vsubq_m_u32 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c > index a17a2741a47..a104a74e259 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c > @@ -1,22 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vsubq_m_u8 (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > return vsubq_m (inactive, a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c > index 10e27dae907..4db52649ab4 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c > @@ -1,21 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16_t b) > { > return vsubq_n_f16 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.f16" } } */ > > +/* > +**foo1: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo1 (float16x8_t a, float16_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.f16" } } */ > +/* > +**foo2: > +** ... > +** vsub.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo2 (float16x8_t a) > +{ > + return vsubq (a, 1.1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c > index 9e16d6c075c..fe97eed7d37 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c > @@ -1,21 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32_t b) > { > return vsubq_n_f32 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.f32" } } */ > > +/* > +**foo1: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo1 (float32x4_t a, float32_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.f32" } } */ > +/* > +**foo2: > +** ... > +** vsub.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo2 (float32x4_t a) > +{ > + return vsubq (a, 1.1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c > index 7f2af8691c0..d695fc83e06 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c > @@ -1,22 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16_t b) > { > return vsubq_n_s16 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i16" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, int16_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c > index a5e6bf486fd..c281e21ab0c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c > @@ -1,22 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32_t b) > { > return vsubq_n_s32 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i32" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, int32_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c > index 5754379358d..ef36b4d6330 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c > @@ -1,22 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8_t b) > { > return vsubq_n_s8 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i8" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, int8_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c > index ea0a3f9260c..be754d894a8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c > @@ -1,22 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16_t b) > { > return vsubq_n_u16 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i16" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, uint16_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i16" } } */ > +/* > +**foo2: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t a) > +{ > + return vsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c > index cc409b59438..ef0aaa4cf08 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c > @@ -1,22 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32_t b) > { > return vsubq_n_u32 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i32" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, uint32_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i32" } } */ > +/* > +**foo2: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t a) > +{ > + return vsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c > index 8a18a89b353..c55aefc3307 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c > @@ -1,22 +1,45 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > -/* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8_t b) > { > return vsubq_n_u8 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i8" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, uint8_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i8" } } */ > +/* > +**foo2: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t a) > +{ > + return vsubq (a, 1); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c > index 15e732f1f66..469395452bd 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16x8_t b) > { > return vsubq_s16 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i16" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo1 (int16x8_t a, int16x8_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c > index 5b4ee855711..0e60e1c6f60 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32x4_t b) > { > return vsubq_s32 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i32" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo1 (int32x4_t a, int32x4_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c > index b23893af605..882d63dfcf7 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8x16_t b) > { > return vsubq_s8 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i8" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo1 (int8x16_t a, int8x16_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c > index edb5e354411..fe9baf3d52c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16x8_t b) > { > return vsubq_u16 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i16" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo1 (uint16x8_t a, uint16x8_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i16" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c > index 68040afd52b..b82051d69d5 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32x4_t b) > { > return vsubq_u32 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i32" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo1 (uint32x4_t a, uint32x4_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i32" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c > index 92c4f059b0e..630b2f79f1f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c > @@ -1,21 +1,33 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8x16_t b) > { > return vsubq_u8 (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i8" } } */ > > +/* > +**foo1: > +** ... > +** vsub.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo1 (uint8x16_t a, uint8x16_t b) > { > return vsubq (a, b); > } > > -/* { dg-final { scan-assembler "vsub.i8" } } */ > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c > index 4cb8be0ea7f..c48bea7e9f0 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16x8_t b, mve_pred16_t p) > { > - return vsubq_x_f16 (a, b, p); > + return vsubq_x_f16 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c > index f6711d7f207..d3e129bb6ee 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32x4_t b, mve_pred16_t p) > { > - return vsubq_x_f32 (a, b, p); > + return vsubq_x_f32 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c > index c4adacbf5be..2dcaff58c09 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float16x8_t > foo (float16x8_t a, float16_t b, mve_pred16_t p) > { > - return vsubq_x_n_f16 (a, b, p); > + return vsubq_x_n_f16 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo1 (float16x8_t a, float16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float16x8_t > +foo2 (float16x8_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1.1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c > index a4affa0a3a9..92bafa3c4cc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > /* { dg-add-options arm_v8_1m_mve_fp } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > float32x4_t > foo (float32x4_t a, float32_t b, mve_pred16_t p) > { > - return vsubq_x_n_f32 (a, b, p); > + return vsubq_x_n_f32 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.f32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo1 (float32x4_t a, float32_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.f32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +float32x4_t > +foo2 (float32x4_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1.1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c > index 99c59b1a6c1..f01e8d7d490 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16_t b, mve_pred16_t p) > { > - return vsubq_x_n_s16 (a, b, p); > + return vsubq_x_n_s16 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int16x8_t > +foo1 (int16x8_t a, int16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c > index 6c29ebec05c..506966424cc 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32_t b, mve_pred16_t p) > { > - return vsubq_x_n_s32 (a, b, p); > + return vsubq_x_n_s32 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int32x4_t > +foo1 (int32x4_t a, int32_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c > index 0f83c305473..3c4a5d8129c 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8_t b, mve_pred16_t p) > { > - return vsubq_x_n_s8 (a, b, p); > + return vsubq_x_n_s8 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +int8x16_t > +foo1 (int8x16_t a, int8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c > index 9a372d762d1..958e5aa2ce8 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16_t b, mve_pred16_t p) > { > - return vsubq_x_n_u16 (a, b, p); > + return vsubq_x_n_u16 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo2 (uint16x8_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c > index 5219f154fa9..ba39c75bb2b 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32_t b, mve_pred16_t p) > { > - return vsubq_x_n_u32 (a, b, p); > + return vsubq_x_n_u32 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo2 (uint32x4_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c > index 0a0bcf8623a..19204d1d80f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c > @@ -1,15 +1,57 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8_t b, mve_pred16_t p) > { > - return vsubq_x_n_u8 (a, b, p); > + return vsubq_x_n_u8 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* > +**foo2: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo2 (uint8x16_t a, mve_pred16_t p) > +{ > + return vsubq_x (a, 1, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c > index 37936a6d647..8dcc5477c6f 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int16x8_t > foo (int16x8_t a, int16x8_t b, mve_pred16_t p) > { > - return vsubq_x_s16 (a, b, p); > + return vsubq_x_s16 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +int16x8_t > +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c > index c085f59c6a2..a2d43323227 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int32x4_t > foo (int32x4_t a, int32x4_t b, mve_pred16_t p) > { > - return vsubq_x_s32 (a, b, p); > + return vsubq_x_s32 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +int32x4_t > +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c > index 361507821ea..8ead3d22439 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > int8x16_t > foo (int8x16_t a, int8x16_t b, mve_pred16_t p) > { > - return vsubq_x_s8 (a, b, p); > + return vsubq_x_s8 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +int8x16_t > +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c > index 21423dc4f80..f0faf8165d2 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint16x8_t > foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) > { > - return vsubq_x_u16 (a, b, p); > + return vsubq_x_u16 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i16" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +uint16x8_t > +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c > index 38dd09ad8f7..67a70931859 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint32x4_t > foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) > { > - return vsubq_x_u32 (a, b, p); > + return vsubq_x_u32 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i32" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +uint32x4_t > +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c > b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c > index 406cbf760fd..19002336cbd 100644 > --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c > @@ -1,15 +1,41 @@ > /* { dg-require-effective-target arm_v8_1m_mve_ok } */ > /* { dg-add-options arm_v8_1m_mve } */ > /* { dg-additional-options "-O2" } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > > #include "arm_mve.h" > > +/* > +**foo: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > uint8x16_t > foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) > { > - return vsubq_x_u8 (a, b, p); > + return vsubq_x_u8 (a, b, p); > } > > -/* { dg-final { scan-assembler "vpst" } } */ > -/* { dg-final { scan-assembler "vsubt.i8" } } */ > > +/* > +**foo1: > +** ... > +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) > +** ... > +** vpst(?: @.*|) > +** ... > +** vsubt.i8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) > +** ... > +*/ > +uint8x16_t > +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) > +{ > + return vsubq_x (a, b, p); > +} > + > +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ > \ No newline at end of file > -- > 2.25.1
RE: [PATCH 19/35] arm: improve tests and fix vsubq*
Kyrylo Tkachov via Gcc-patches Tue, 22 Nov 2022 08:52:33 -0800
- Re: [PATCH 16/35] arm: Add integer... Andrea Corallo via Gcc-patches
- RE: [PATCH 16/35] arm: Add integer vec... Kyrylo Tkachov via Gcc-patches
- [PATCH 27/35] arm: improve tests for vqaddq... Andrea Corallo via Gcc-patches
- RE: [PATCH 27/35] arm: improve tests f... Kyrylo Tkachov via Gcc-patches
- [PATCH 33/35] arm: improve tests and fix vr... Andrea Corallo via Gcc-patches
- [PATCH 24/35] arm: improve tests for vmlada... Andrea Corallo via Gcc-patches
- RE: [PATCH 24/35] arm: improve tests f... Kyrylo Tkachov via Gcc-patches
- [PATCH 23/35] arm: improve tests for viwdup... Andrea Corallo via Gcc-patches
- RE: [PATCH 23/35] arm: improve tests f... Kyrylo Tkachov via Gcc-patches
- [PATCH 19/35] arm: improve tests and fix vs... Andrea Corallo via Gcc-patches
- RE: [PATCH 19/35] arm: improve tests a... Kyrylo Tkachov via Gcc-patches
- [PATCH 30/35] arm: improve tests for vqrdml... Andrea Corallo via Gcc-patches
- RE: [PATCH 30/35] arm: improve tests f... Kyrylo Tkachov via Gcc-patches
- [PATCH 08/35] arm: improve tests for vmin* Andrea Corallo via Gcc-patches
- RE: [PATCH 08/35] arm: improve tests f... Kyrylo Tkachov via Gcc-patches
- [PATCH 22/35] arm: improve tests for vhsubq... Andrea Corallo via Gcc-patches
- RE: [PATCH 22/35] arm: improve tests f... Kyrylo Tkachov via Gcc-patches
- [PATCH 25/35] arm: improve tests and fix vm... Andrea Corallo via Gcc-patches
- RE: [PATCH 25/35] arm: improve tests a... Kyrylo Tkachov via Gcc-patches
- [PATCH 28/35] arm: improve tests for vqdmla... Andrea Corallo via Gcc-patches
- RE: [PATCH 28/35] arm: improve tests f... Kyrylo Tkachov via Gcc-patches