LGTM
On Mon, Dec 19, 2022 at 9:12 AM Christoph Muellner
<christoph.muell...@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muell...@vrull.eu>
>
> This patch adds support for the XTheadBs ISA extension.
> The new INSN pattern is defined in a new file to separate
> this vendor extension from the standard extensions.
> The cost model adjustment reuses the xbs:bext cost.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost.
> * config/riscv/thead.md (*th_tst): New INSN.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/xtheadbs-tst.c: New test.
>
> Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
> ---
> gcc/config/riscv/riscv.cc | 4 ++--
> gcc/config/riscv/thead.md | 11 +++++++++++
> gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 +++++++++++++
> 3 files changed, 26 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index a8d5e1dac7f..537515771c6 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2400,8 +2400,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
> outer_code, int opno ATTRIBUTE_UN
> *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
> return true;
> }
> - /* bext pattern for zbs. */
> - if (TARGET_ZBS && outer_code == SET
> + /* bit extraction pattern (zbs:bext, xtheadbs:tst). */
> + if ((TARGET_ZBS || TARGET_XTHEADBS) && outer_code == SET
> && GET_CODE (XEXP (x, 1)) == CONST_INT
> && INTVAL (XEXP (x, 1)) == 1)
> {
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index 0257cbfad3e..0e23644ef59 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -29,3 +29,14 @@ (define_insn "*th_addsl"
> "th.addsl\t%0,%1,%3,%2"
> [(set_attr "type" "bitmanip")
> (set_attr "mode" "<X:MODE>")])
> +
> +;; XTheadBs
> +
> +(define_insn "*th_tst"
> + [(set (match_operand:X 0 "register_operand" "=r")
> + (zero_extract:X (match_operand:X 1 "register_operand" "r")
> + (const_int 1)
> + (match_operand 2 "immediate_operand" "i")))]
> + "TARGET_XTHEADBS"
> + "th.tst\t%0,%1,%2"
> + [(set_attr "type" "bitmanip")])
> diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
> b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
> new file mode 100644
> index 00000000000..674cec09128
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gc_xtheadbs" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
> +
> +long
> +foo1 (long i)
> +{
> + return 1L & (i >> 20);
> +}
> +
> +/* { dg-final { scan-assembler-times "th.tst\t" 1 } } */
> +/* { dg-final { scan-assembler-not "andi" } } */
> --
> 2.38.1
>
