LGTM
On Mon, Dec 19, 2022 at 9:08 AM Christoph Muellner
<christoph.muell...@vrull.eu> wrote:
>
> From: Christoph Müllner <christoph.muell...@vrull.eu>
>
> This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
> The C906 is shipped for quite some time (it is the core of the Allwinner D1).
> Note, that the tuning struct for the C906 is already part of GCC (it is
> also name "thead-c906").
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/mcpu-thead-c906.c: New test.
>
> Changes for v2:
> - Enable all supported vendor extensions
>
> Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
> ---
> gcc/config/riscv/riscv-cores.def | 4 +++
> .../gcc.target/riscv/mcpu-thead-c906.c | 28 +++++++++++++++++++
> 2 files changed, 32 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
>
> diff --git a/gcc/config/riscv/riscv-cores.def
> b/gcc/config/riscv/riscv-cores.def
> index 31ad34682c5..307381802fa 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -73,4 +73,8 @@ RISCV_CORE("sifive-s76", "rv64imafdc",
> "sifive-7-series")
> RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
> RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
>
> +RISCV_CORE("thead-c906",
> "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
> + "xtheadcondmov_xtheadfmemidx_xtheadmac_"
> + "xtheadmemidx_xtheadmempair_xtheadsync",
> + "thead-c906")
> #undef RISCV_CORE
> diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
> b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
> new file mode 100644
> index 00000000000..a71b43a6167
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
> +/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */
> +/* T-Head XuanTie C906 => rv64imafdc */
> +
> +#if !((__riscv_xlen == 64) \
> + && !defined(__riscv_32e) \
> + && defined(__riscv_mul) \
> + && defined(__riscv_atomic) \
> + && (__riscv_flen == 64) \
> + && defined(__riscv_compressed) \
> + && defined(__riscv_xtheadba) \
> + && defined(__riscv_xtheadbb) \
> + && defined(__riscv_xtheadbs) \
> + && defined(__riscv_xtheadcmo) \
> + && defined(__riscv_xtheadcondmov) \
> + && defined(__riscv_xtheadfmemidx) \
> + && defined(__riscv_xtheadmac) \
> + && defined(__riscv_xtheadmemidx) \
> + && defined(__riscv_xtheadmempair) \
> + && defined(__riscv_xtheadsync))
> +#error "unexpected arch"
> +#endif
> +
> +int main()
> +{
> + return 0;
> +}
> --
> 2.38.1
>
