Richard Biener <rguent...@suse.de> writes:
> On Tue, 11 Apr 2023, Richard Sandiford wrote:
>
>> <juzhe.zh...@rivai.ai> writes:
>> > ARM SVE has?svint8_t, svint8x2_t, svint8x3_t, svint8x4_t
>> > As far as I known, they don't have tuple type for partial vector.
>>
>> Yeah, there are no separate types for partial vectors, but there
>> are separate modes. E.g. VNx2QI is a partial vector of QIs,
>> with each QI stored in a 64-bit container.
>>
>> I agree with all the comments about the danger of growing the number of
>> modes too much. But it looks like rtx_def should be easy to rearrange.
>> Unless I'm missing something, there are less than 256 rtx codes at
>> present. So one simple option would be to make the code 8 bits and
>> the machine_mode 16 bits (and swap them, so that they stay well-aligned
>> wrt their size).
>
> But then the bigger issue is tree_type_common where we agreed to
> bump precision from 10 to 16 bits, with bumping machine_mode from
> 8 to 16 we then are left with only 3 spare bits from 15 now - if
> the comments are correct.
Hmm, true. I guess the two options are:
(1) Increase the size of the machine_mode field by the smallest amount
possible (accepting that it will be non-power-of-2). I'd be
surprised if that's a significant performance issue, since modes
aren't as fundamental to trees as rtxes (and since a non-power-of-2
precision doesn't seem to have hurt).
(2) Increase the size to 16 anyway, with the understanding that the
mode is the first thing to shrink if we need a fourth spare bit.
> In tree_decl_common we have 13 unused bits.
>
> IRA allocno would also increase and it's hard_regno field looks
> suspiciously unaligned already (unless unsigned/signed re-aligns
> bitfields).
Yeah, agree it looks unaligned.
If I've read it correctly, it looks like there's a 32-bit gap
on 64-bit hosts before objects[2]. So perhaps we could move
the mode fields there and put hard_regno where the modes are now.
Thanks,
Richard
