On Wed, 12 Apr 2023, Kito Cheng wrote: > Hi Richard: > > > > In order to model LMUL in backend, we have to the combination of > > > scalar type and LMUL; possible LMUL is 1, 2, 4, 8, 1/2, 1/4, 1/8 - 8 > > > different types of LMUL, and we'll have QI, HI, SI, DI, HF, SF and DF, > > > so basically we'll have 7 (LMUL type) * 7 (scalar type) here. > > > > Other archs have load/store-multiple instructions, IIRC those > > are modeled with the appropriate set of operands. Do RVV LMUL > > group inputs/outputs overlap with the non-LMUL grouped registers > > and can they be used as aliases or is this supposed to be > > implemented transparently on the register file level only? > > LMUL and non-LMUL (or LMUL=1) modes use the same vector register file. > > Reg for LMUL=1/2 : { {v0, v1, ...v31} } > Reg for LMUL=1 : { {v0, v1, ...v31} } > Reg for LMUL=2 : { {v0, v1}, {v2, v3}, ... {v30, v31} } // reg. must > align to multiple of 2. > Reg for LMUL=4 : { {v0, v1, v2, v3}, {v4, v5, v6, v7}, ... {v28, v29, > v30, v31} } // reg. must align to multiple of 4. > .. > Reg for 2-tuples of LMUL=1 : { {v0, v1}, {v1, v2}, ... {v29, v30}, {v30, v31} > } > Reg for 2-tuples of LMUL=2 : { {v0, v1, v2, v3}, {v2, v3, v4, v5}, ... > {v28, v29, v30, v31}, {v28, v29, v30, v31} } // reg. must align to > multiple of 2. > ... > > > But yes, implementing this as operations on multi-register > > ops with large modes is probably the only sensible approach. > > > > I don't see how LMUL of 1/2, 1/4 or 1/8 is useful though? Can you > > explain? Is that supposed to virtually increase the number of > > registers? How do you represent r0:1/8:0 vs r0:1/8:3 (the first > > and the third "virtual" register decomposed from r0) in GCC? To > > me the natural way would be a subreg of r0? > > > > Somehow RVV seems to have more knobs than necessary for tuning > > the actual vector register layout (aka N axes but only N-1 dimensions > > thus the axes are > > The concept of fractional LMUL is the same as the concept of AArch64's > partial SVE vectors, > so they can only access the lowest part, like SVE's partial vector. > > We want to spill/restore the exact size of those modes (1/2, 1/4, > 1/8), so adding dedicated modes for those partial vector modes should > be unavoidable IMO. > > And even if we use sub-vector, we still need to define those partial > vector types.
Could you use integer modes for the fractional vectors? For computation you can always appropriately limit the LEN?