Factorize vandq, veorq, vorrq, vbicq so that they use the same
parameterized names.
2022-09-08 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_INT_M_BINARY_LOGIC)
(MVE_FP_M_BINARY_LOGIC): New.
(MVE_INT_M_N_BINARY_LOGIC): New.
(MVE_INT_N_BINARY_LOGIC): New.
(mve_insn): Add vand, veor, vorr, vbic.
* config/arm/mve.md (mve_vandq_m_<supf><mode>)
(mve_veorq_m_<supf><mode>, mve_vorrq_m_<supf><mode>)
(mve_vbicq_m_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
(mve_vandq_m_f<mode>, mve_veorq_m_f<mode>, mve_vorrq_m_f<mode>)
(mve_vbicq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
(mve_vorrq_n_<supf><mode>)
(mve_vbicq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vorrq_m_n_<supf><mode>, mve_vbicq_m_n_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 32 +++++++
gcc/config/arm/mve.md | 161 +++++-------------------------------
2 files changed, 51 insertions(+), 142 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index d3bef594775..b0ea1af77d2 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -339,24 +339,48 @@ (define_int_iterator MVE_INT_M_BINARY [
VSUBQ_M_S VSUBQ_M_U
])
+(define_int_iterator MVE_INT_M_BINARY_LOGIC [
+ VANDQ_M_S VANDQ_M_U
+ VBICQ_M_S VBICQ_M_U
+ VEORQ_M_S VEORQ_M_U
+ VORRQ_M_S VORRQ_M_U
+ ])
+
(define_int_iterator MVE_INT_M_N_BINARY [
VADDQ_M_N_S VADDQ_M_N_U
VMULQ_M_N_S VMULQ_M_N_U
VSUBQ_M_N_S VSUBQ_M_N_U
])
+(define_int_iterator MVE_INT_M_N_BINARY_LOGIC [
+ VBICQ_M_N_S VBICQ_M_N_U
+ VORRQ_M_N_S VORRQ_M_N_U
+ ])
+
(define_int_iterator MVE_INT_N_BINARY [
VADDQ_N_S VADDQ_N_U
VMULQ_N_S VMULQ_N_U
VSUBQ_N_S VSUBQ_N_U
])
+(define_int_iterator MVE_INT_N_BINARY_LOGIC [
+ VBICQ_N_S VBICQ_N_U
+ VORRQ_N_S VORRQ_N_U
+ ])
+
(define_int_iterator MVE_FP_M_BINARY [
VADDQ_M_F
VMULQ_M_F
VSUBQ_M_F
])
+(define_int_iterator MVE_FP_M_BINARY_LOGIC [
+ VANDQ_M_F
+ VBICQ_M_F
+ VEORQ_M_F
+ VORRQ_M_F
+ ])
+
(define_int_iterator MVE_FP_M_N_BINARY [
VADDQ_M_N_F
VMULQ_M_N_F
@@ -379,9 +403,17 @@ (define_int_attr mve_insn [
(VADDQ_M_N_S "vadd") (VADDQ_M_N_U "vadd") (VADDQ_M_N_F "vadd")
(VADDQ_M_S "vadd") (VADDQ_M_U "vadd") (VADDQ_M_F "vadd")
(VADDQ_N_S "vadd") (VADDQ_N_U "vadd") (VADDQ_N_F "vadd")
+ (VANDQ_M_S "vand") (VANDQ_M_U "vand") (VANDQ_M_F "vand")
+ (VBICQ_M_N_S "vbic") (VBICQ_M_N_U "vbic")
+ (VBICQ_M_S "vbic") (VBICQ_M_U "vbic") (VBICQ_M_F "vbic")
+ (VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
+ (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor")
(VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul")
(VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul")
(VMULQ_N_S "vmul") (VMULQ_N_U "vmul") (VMULQ_N_F "vmul")
+ (VORRQ_M_N_S "vorr") (VORRQ_M_N_U "vorr")
+ (VORRQ_M_S "vorr") (VORRQ_M_U "vorr") (VORRQ_M_F "vorr")
+ (VORRQ_N_S "vorr") (VORRQ_N_U "vorr")
(VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
(VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
(VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index ccb3cf23304..fbae1d3791f 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1805,21 +1805,6 @@ (define_insn "mve_vbicq_f<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vbicq_n_s, vbicq_n_u])
-;;
-(define_insn "mve_vbicq_n_<supf><mode>"
- [
- (set (match_operand:MVE_5 0 "s_register_operand" "=w")
- (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")]
- VBICQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vbic.i%#<V_sz_elem> %q0, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vcaddq, vcaddq_rot90, vcadd_rot180, vcadd_rot270])
;;
@@ -2191,17 +2176,18 @@ (define_insn "mve_vorrq_f<mode>"
])
;;
+;; [vbicq_n_s, vbicq_n_u])
;; [vorrq_n_u, vorrq_n_s])
;;
-(define_insn "mve_vorrq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")]
- VORRQ_N))
+ MVE_INT_N_BINARY_LOGIC))
]
"TARGET_HAVE_MVE"
- "vorr.i%#<V_sz_elem> %q0, %2"
+ "<mve_insn>.i%#<V_sz_elem> %q0, %2"
[(set_attr "type" "mve_move")
])
@@ -2445,21 +2431,6 @@ (define_insn "mve_vrmlaldavhq_<supf>v4si"
[(set_attr "type" "mve_move")
])
-;;
-;; [vbicq_m_n_s, vbicq_m_n_u])
-;;
-(define_insn "mve_vbicq_m_n_<supf><mode>"
- [
- (set (match_operand:MVE_5 0 "s_register_operand" "=w")
- (unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
- (match_operand:SI 2 "immediate_operand" "i")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VBICQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vbict.i%#<V_sz_elem> %q0, %2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
;;
;; [vcmpeqq_m_f])
;;
@@ -4269,20 +4240,22 @@ (define_insn "mve_vnegq_m_f<mode>"
(set_attr "length""8")])
;;
+;; [vbicq_m_n_s, vbicq_m_n_u])
;; [vorrq_m_n_s, vorrq_m_n_u])
;;
-(define_insn "mve_vorrq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:MVE_5 0 "s_register_operand" "=w")
(unspec:MVE_5 [(match_operand:MVE_5 1 "s_register_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VORRQ_M_N))
+ MVE_INT_M_N_BINARY_LOGIC))
]
"TARGET_HAVE_MVE"
- "vpst\;vorrt.i%#<V_sz_elem> %q0, %2"
+ "vpst\;<mve_insn>t.i%#<V_sz_elem> %q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
+
;;
;; [vpselq_f])
;;
@@ -5001,35 +4974,21 @@ (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
;;
;; [vandq_m_u, vandq_m_s])
-;;
-(define_insn "mve_vandq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VANDQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vandt %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
;; [vbicq_m_u, vbicq_m_s])
+;; [veorq_m_u, veorq_m_s])
+;; [vorrq_m_u, vorrq_m_s])
;;
-(define_insn "mve_vbicq_m_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VBICQ_M))
+ MVE_INT_M_BINARY_LOGIC))
]
"TARGET_HAVE_MVE"
- "vpst\;vbict %q0, %q2, %q3"
+ "vpst\;<mve_insn>t %q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -5084,23 +5043,6 @@ (define_insn "mve_vcaddq_rot90_m_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [veorq_m_s, veorq_m_u])
-;;
-(define_insn "mve_veorq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VEORQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;veort %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vhaddq_m_n_s, vhaddq_m_n_u])
;;
@@ -5322,23 +5264,6 @@ (define_insn "mve_vornq_m_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vorrq_m_s, vorrq_m_u])
-;;
-(define_insn "mve_vorrq_m_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VORRQ_M))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vorrt %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vqaddq_m_n_u, vqaddq_m_n_s])
;;
@@ -6483,35 +6408,21 @@ (define_insn "@mve_<mve_insn>q_m_n_f<mode>"
;;
;; [vandq_m_f])
-;;
-(define_insn "mve_vandq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VANDQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vandt %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
;; [vbicq_m_f])
+;; [veorq_m_f])
+;; [vorrq_m_f])
;;
-(define_insn "mve_vbicq_m_f<mode>"
+(define_insn "@mve_<mve_insn>q_m_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:MVE_0 2 "s_register_operand" "w")
(match_operand:MVE_0 3 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VBICQ_M_F))
+ MVE_FP_M_BINARY_LOGIC))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vbict %q0, %q2, %q3"
+ "vpst\;<mve_insn>t %q0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -6702,23 +6613,6 @@ (define_insn "mve_vcmulq_rot90_m_f<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [veorq_m_f])
-;;
-(define_insn "mve_veorq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VEORQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;veort %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vfmaq_m_f])
;;
@@ -6838,23 +6732,6 @@ (define_insn "mve_vornq_m_f<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vorrq_m_f])
-;;
-(define_insn "mve_vorrq_m_f<mode>"
- [
- (set (match_operand:MVE_0 0 "s_register_operand" "=w")
- (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
- (match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:MVE_0 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VORRQ_M_F))
- ]
- "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vorrt %q0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vstrbq_s vstrbq_u]
;;
--
2.34.1
