Factorize vhaddq_m_n, vhsubq_m_n, vmlaq_m_n, vmlasq_m_n, vqaddq_m_n, vqdmlahq_m_n, vqdmlashq_m_n, vqdmulhq_m_n, vqrdmlahq_m_n, vqrdmlashq_m_n, vqrdmulhq_m_n, vqsubq_m_n so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.l...@arm.com> gcc/ * config/arm/iterators.md (MVE_INT_SU_M_N_BINARY): New. (mve_insn): Add vhaddq, vhsubq, vmlaq, vmlasq, vqaddq, vqdmlahq, vqdmlashq, vqdmulhq, vqrdmlahq, vqrdmlashq, vqrdmulhq, vqsubq. (supf): Add VQDMLAHQ_M_N_S, VQDMLASHQ_M_N_S, VQRDMLAHQ_M_N_S, VQRDMLASHQ_M_N_S, VQDMULHQ_M_N_S, VQRDMULHQ_M_N_S. * config/arm/mve.md (mve_vhaddq_m_n_<supf><mode>) (mve_vhsubq_m_n_<supf><mode>, mve_vmlaq_m_n_<supf><mode>) (mve_vmlasq_m_n_<supf><mode>, mve_vqaddq_m_n_<supf><mode>) (mve_vqdmlahq_m_n_s<mode>, mve_vqdmlashq_m_n_s<mode>) (mve_vqrdmlahq_m_n_s<mode>, mve_vqrdmlashq_m_n_s<mode>) (mve_vqsubq_m_n_<supf><mode>, mve_vqdmulhq_m_n_s<mode>) (mve_vqrdmulhq_m_n_s<mode>): Merge into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this. --- gcc/config/arm/iterators.md | 33 ++++++ gcc/config/arm/mve.md | 202 +++--------------------------------- 2 files changed, 46 insertions(+), 189 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 6dbc40f842c..60452cdefe3 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -384,6 +384,21 @@ (define_int_iterator MVE_INT_M_N_BINARY_LOGIC [ VORRQ_M_N_S VORRQ_M_N_U ]) +(define_int_iterator MVE_INT_SU_M_N_BINARY [ + VHADDQ_M_N_S VHADDQ_M_N_U + VHSUBQ_M_N_S VHSUBQ_M_N_U + VMLAQ_M_N_S VMLAQ_M_N_U + VMLASQ_M_N_S VMLASQ_M_N_U + VQDMLAHQ_M_N_S + VQDMLASHQ_M_N_S + VQRDMLAHQ_M_N_S + VQRDMLASHQ_M_N_S + VQADDQ_M_N_S VQADDQ_M_N_U + VQSUBQ_M_N_S VQSUBQ_M_N_U + VQDMULHQ_M_N_S + VQRDMULHQ_M_N_S + ]) + (define_int_iterator MVE_INT_N_BINARY [ VADDQ_N_S VADDQ_N_U VMULQ_N_S VMULQ_N_U @@ -450,12 +465,16 @@ (define_int_attr mve_insn [ (VBICQ_N_S "vbic") (VBICQ_N_U "vbic") (VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F "vcreate") (VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor") + (VHADDQ_M_N_S "vhadd") (VHADDQ_M_N_U "vhadd") (VHADDQ_M_S "vhadd") (VHADDQ_M_U "vhadd") (VHADDQ_N_S "vhadd") (VHADDQ_N_U "vhadd") + (VHSUBQ_M_N_S "vhsub") (VHSUBQ_M_N_U "vhsub") (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub") (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub") (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax") (VMINQ_M_S "vmin") (VMINQ_M_U "vmin") + (VMLAQ_M_N_S "vmla") (VMLAQ_M_N_U "vmla") + (VMLASQ_M_N_S "vmlas") (VMLASQ_M_N_U "vmlas") (VMULHQ_M_S "vmulh") (VMULHQ_M_U "vmulh") (VMULQ_M_N_S "vmul") (VMULQ_M_N_U "vmul") (VMULQ_M_N_F "vmul") (VMULQ_M_S "vmul") (VMULQ_M_U "vmul") (VMULQ_M_F "vmul") @@ -463,22 +482,30 @@ (define_int_attr mve_insn [ (VORRQ_M_N_S "vorr") (VORRQ_M_N_U "vorr") (VORRQ_M_S "vorr") (VORRQ_M_U "vorr") (VORRQ_M_F "vorr") (VORRQ_N_S "vorr") (VORRQ_N_U "vorr") + (VQADDQ_M_N_S "vqadd") (VQADDQ_M_N_U "vqadd") (VQADDQ_M_S "vqadd") (VQADDQ_M_U "vqadd") (VQADDQ_N_S "vqadd") (VQADDQ_N_U "vqadd") (VQDMLADHQ_M_S "vqdmladh") (VQDMLADHXQ_M_S "vqdmladhx") + (VQDMLAHQ_M_N_S "vqdmlah") + (VQDMLASHQ_M_N_S "vqdmlash") (VQDMLSDHQ_M_S "vqdmlsdh") (VQDMLSDHXQ_M_S "vqdmlsdhx") + (VQDMULHQ_M_N_S "vqdmulh") (VQDMULHQ_M_S "vqdmulh") (VQDMULHQ_N_S "vqdmulh") (VQRDMLADHQ_M_S "vqrdmladh") (VQRDMLADHXQ_M_S "vqrdmladhx") + (VQRDMLAHQ_M_N_S "vqrdmlah") + (VQRDMLASHQ_M_N_S "vqrdmlash") (VQRDMLSDHQ_M_S "vqrdmlsdh") (VQRDMLSDHXQ_M_S "vqrdmlsdhx") + (VQRDMULHQ_M_N_S "vqrdmulh") (VQRDMULHQ_M_S "vqrdmulh") (VQRDMULHQ_N_S "vqrdmulh") (VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl") (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl") + (VQSUBQ_M_N_S "vqsub") (VQSUBQ_M_N_U "vqsub") (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub") (VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub") (VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd") @@ -1636,6 +1663,12 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VQRDMULHQ_M_S "s") (VQDMULHQ_N_S "s") (VQRDMULHQ_N_S "s") + (VQDMLAHQ_M_N_S "s") + (VQDMLASHQ_M_N_S "s") + (VQRDMLAHQ_M_N_S "s") + (VQRDMLASHQ_M_N_S "s") + (VQDMULHQ_M_N_S "s") + (VQRDMULHQ_M_N_S "s") ]) ;; Both kinds of return insn. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 3377e03ee06..d14a04d5f82 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -4982,35 +4982,29 @@ (define_insn "mve_vcaddq_rot90_m_<supf><mode>" ;; ;; [vhaddq_m_n_s, vhaddq_m_n_u]) -;; -(define_insn "mve_vhaddq_m_n_<supf><mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VHADDQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vhaddt.<supf>%#<V_sz_elem> %q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; ;; [vhsubq_m_n_s, vhsubq_m_n_u]) +;; [vmlaq_m_n_s, vmlaq_m_n_u]) +;; [vmlasq_m_n_u, vmlasq_m_n_s]) +;; [vqaddq_m_n_u, vqaddq_m_n_s]) +;; [vqdmlahq_m_n_s]) +;; [vqdmlashq_m_n_s]) +;; [vqdmulhq_m_n_s]) +;; [vqrdmlahq_m_n_s]) +;; [vqrdmlashq_m_n_s]) +;; [vqrdmulhq_m_n_s]) +;; [vqsubq_m_n_u, vqsubq_m_n_s]) ;; -(define_insn "mve_vhsubq_m_n_<supf><mode>" +(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") (match_operand:<V_elem> 3 "s_register_operand" "r") (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VHSUBQ_M_N)) + MVE_INT_SU_M_N_BINARY)) ] "TARGET_HAVE_MVE" - "vpst\;vhsubt.<supf>%#<V_sz_elem> %q0, %q2, %3" + "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5032,40 +5026,6 @@ (define_insn "mve_vmladavaq_p_<supf><mode>" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vmlaq_m_n_s, vmlaq_m_n_u]) -;; -(define_insn "mve_vmlaq_m_n_<supf><mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VMLAQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vmlat.<supf>%#<V_sz_elem> %q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vmlasq_m_n_u, vmlasq_m_n_s]) -;; -(define_insn "mve_vmlasq_m_n_<supf><mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VMLASQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vmlast.<supf>%#<V_sz_elem> %q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vmullbq_int_m_u, vmullbq_int_m_s]) ;; @@ -5117,91 +5077,6 @@ (define_insn "mve_vornq_m_<supf><mode>" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vqaddq_m_n_u, vqaddq_m_n_s]) -;; -(define_insn "mve_vqaddq_m_n_<supf><mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VQADDQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqaddt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vqdmlahq_m_n_s]) -;; -(define_insn "mve_vqdmlahq_m_n_s<mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VQDMLAHQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vqdmlashq_m_n_s]) -;; -(define_insn "mve_vqdmlashq_m_n_s<mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VQDMLASHQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vqrdmlahq_m_n_s]) -;; -(define_insn "mve_vqrdmlahq_m_n_s<mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VQRDMLAHQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqrdmlaht.s%#<V_sz_elem>\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vqrdmlashq_m_n_s]) -;; -(define_insn "mve_vqrdmlashq_m_n_s<mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VQRDMLASHQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqrdmlasht.s%#<V_sz_elem>\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vqshlq_m_n_s, vqshlq_m_n_u]) ;; @@ -5219,23 +5094,6 @@ (define_insn "mve_vqshlq_m_n_<supf><mode>" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vqsubq_m_n_u, vqsubq_m_n_s]) -;; -(define_insn "mve_vqsubq_m_n_<supf><mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VQSUBQ_M_N)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqsubt.<supf>%#<V_sz_elem>\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vrshrq_m_n_s, vrshrq_m_n_u]) ;; @@ -5389,40 +5247,6 @@ (define_insn "mve_vmlsdavaxq_p_s<mode>" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vqdmulhq_m_n_s]) -;; -(define_insn "mve_vqdmulhq_m_n_s<mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VQDMULHQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqdmulht.s%#<V_sz_elem>\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vqrdmulhq_m_n_s]) -;; -(define_insn "mve_vqrdmulhq_m_n_s<mode>" - [ - (set (match_operand:MVE_2 0 "s_register_operand" "=w") - (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") - (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:<V_elem> 3 "s_register_operand" "r") - (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")] - VQRDMULHQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqrdmulht.s%#<V_sz_elem>\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vmlaldavaq_p_u, vmlaldavaq_p_s]) ;; -- 2.34.1