Robin Dapp <rdapp....@gmail.com> writes: >> Sorry, only realised later, but: if the precision can cover fewer >> bytes than the bitsize, I suppose there ought to be some zero-byte >> padding at the end as well. > It looks like this problem, and also the padding, has been discussed > before when the precision of VNx1BI etc. was first adjusted in the > RISC-V backend?
Very probably. Can't remember now. > I didn't immediately get the padding, though. So if we e.g. have a > VNx2BI constant {0, 1} what would we pad the resulting value "2" to? > A full byte? Yeah, that part is OK, and was the case I was thinking about when I said OK yesterday. But now that we allow BITSIZE != PRECISION, it's possible for BITSIZE - PRECISION to be more than a full byte, in which case the new loop would not initialise every byte of the mode. I vaguely remembered that that could happen for RVV_FIXED_VLMAX, but perhaps I misremember. If it can't happen then an assert would be OK instead. Thanks, Richard