Yes, we have no choice since DSE is base on BYTESIZE.

So I walk around in RISC-V backend making VNx1BI, VNx2BI, VNx4BI precision 
different with VNx8BI to prevent incorrect DSE.
I think such issue can be addressed when we adjust everything using BITSIZE 
instead of BYTESIZE but it may change to much.
I prefer it to be GCC-15 (such issue can be walk around in RISC-V backend) 
since we have to much things need to be landed in GCC-14.

Thanks.


juzhe.zh...@rivai.ai
 
From: Robin Dapp
Date: 2023-06-29 16:53
To: juzhe.zh...@rivai.ai; gcc-patches; jeffreyalaw; kito.cheng; Kito.cheng; 
palmer; palmer; richard.sandiford
CC: rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for 
VNx1BI, VNx2BI and VNx4BI
>>> are we absolutely sure this is the only problem we will have
>>> with precision != bitsize and it is confined to the backend?
> Yes.
 
With vinfo.vector_mode == VNx4SI
mask_type = get_mask_type_for_scalar_type (vinfo, int)
mask_type is:
vector(4) <signed-boolean:2>
 
I.e. the precision is 2.  This is definitely fishy and related
to the same problem.  I would almost bet that something in the
middle-end relies on the precision for some optimization but
we just haven't hit it yet.
 
Then we have
vector(2) <signed-boolean:4> (precision 4)
as a mask type for vector(2) long int.
 
Likewise we would likely have a precision of 8 for a vector(1)?
Those might be less severe but still...
 
And that's just what I'm seeing spontaneously after like five
minutes.
 
Regards
Robin
 

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