Hello David. Thanks for the patch.
OK. > In the BPF pseudo-c assembly dialect, registers treated as 32-bits > rather than the full 64 in various instructions ought to be printed as > "wN" rather than "rN". But bpf_print_register () was only doing this > for specifically SImode registers, meaning smaller modes were printed > incorrectly. > > This caused assembler errors like: > > Error: unrecognized instruction `w2 =(s8)r1' > > for a 32-bit sign-extending register move instruction, where the source > register is used in QImode. > > Fix bpf_print_register () to print the "w" version of register when > specified by the template for any mode 32-bits or smaller. > > Tested on bpf-unknown-none. > > PR target/111029 > > gcc/ > * config/bpf/bpf.cc (bpf_print_register): Print 'w' registers > for any mode 32-bits or smaller, not just SImode. > > gcc/testsuite/ > > * gcc.target/bpf/smov-2.c: New test. > * gcc.target/bpf/smov-pseudoc-2.c: New test. > --- > gcc/config/bpf/bpf.cc | 2 +- > gcc/testsuite/gcc.target/bpf/smov-2.c | 15 +++++++++++++++ > gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c | 15 +++++++++++++++ > 3 files changed, 31 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/bpf/smov-2.c > create mode 100644 gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c > > diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc > index 3516b79bce4..1d0abd7fbb3 100644 > --- a/gcc/config/bpf/bpf.cc > +++ b/gcc/config/bpf/bpf.cc > @@ -753,7 +753,7 @@ bpf_print_register (FILE *file, rtx op, int code) > fprintf (file, "%s", reg_names[REGNO (op)]); > else > { > - if (code == 'w' && GET_MODE (op) == SImode) > + if (code == 'w' && GET_MODE_SIZE (GET_MODE (op)) <= 4) > { > if (REGNO (op) == BPF_FP) > fprintf (file, "w10"); > diff --git a/gcc/testsuite/gcc.target/bpf/smov-2.c > b/gcc/testsuite/gcc.target/bpf/smov-2.c > new file mode 100644 > index 00000000000..6f3516d2385 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/bpf/smov-2.c > @@ -0,0 +1,15 @@ > +/* Check signed 32-bit mov instructions. */ > +/* { dg-do compile } */ > +/* { dg-options "-mcpu=v4 -O2" } */ > + > +int > +foo (unsigned char a, unsigned short b) > +{ > + int x = (char) a; > + int y = (short) b; > + > + return x + y; > +} > + > +/* { dg-final { scan-assembler {movs32\t%r.,%r.,8\n} } } */ > +/* { dg-final { scan-assembler {movs32\t%r.,%r.,16\n} } } */ > diff --git a/gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c > b/gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c > new file mode 100644 > index 00000000000..6af6cadf8df > --- /dev/null > +++ b/gcc/testsuite/gcc.target/bpf/smov-pseudoc-2.c > @@ -0,0 +1,15 @@ > +/* Check signed 32-bit mov instructions (pseudo-C asm dialect). */ > +/* { dg-do compile } */ > +/* { dg-options "-mcpu=v4 -O2 -masm=pseudoc" } */ > + > +int > +foo (unsigned char a, unsigned short b) > +{ > + int x = (char) a; > + int y = (short) b; > + > + return x + y; > +} > + > +/* { dg-final { scan-assembler {w. = \(s8\) w.\n} } } */ > +/* { dg-final { scan-assembler {w. = \(s16\) w.\n} } } */