Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

[Robin Dapp]

On 11/13/23 10:38, juzhe.zh...@rivai.ai wrote:
> For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout
> the entire function, and could validly be replaced in all its
> occurrences by @var{op}.  (``Validly'' here refers to the data flow of
> the program; simple replacement may make some insns invalid.)  For
> example, when a constant is loaded into a register that is never
> assigned any other value, this kind of note is used.
> 
> I think REG_QEUIV is what I want. So I think you can test it to see if there 
> is regression on current tests.

Let's keep the REG_EQUAL optimization for later in case we find
a case that triggers it.

Regards
 Robin

Subject: [PATCH v2] RISC-V: vsetvl: Refine REG_EQUAL equality.

This patch enhances the equality check for REG_EQUAL notes in the vsetvl
pass by using the == operator instead of rtx_equal_p.  With that, in
situations like the following, a5 and a7 are not considered equal
anymore.

(insn 62 60 63 4 (set (reg:DI 17 a7 [orig:154 loop_len_54 ] [154])
        (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (reg:DI 30 t5 [219]))) 442 {umindi3}
     (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (const_int 8 [0x8]))
        (nil)))
(insn 63 62 65 4 (set (reg:DI 15 a5 [orig:175 _103 ] [175])
        (minus:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (reg:DI 17 a7 [orig:154 loop_len_54 ] [154]))) 11 {subdi3}
     (nil))
(insn 65 63 66 4 (set (reg:DI 16 a6 [orig:153 loop_len_53 ] [153])
        (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
            (reg:DI 30 t5 [219]))) 442 {umindi3}
     (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
            (const_int 8 [0x8]))
        (nil)))

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc (source_equal_p): Use pointer
        equality for REG_EQUAL.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c: New 
test.
---
 gcc/config/riscv/riscv-vsetvl.cc              | 12 +++++++++++-
 .../partial/multiple_rgroup_zbb_run-2.c       | 19 +++++++++++++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 3fa25a6404d..0eea33dd0e1 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -561,7 +561,17 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
   rtx note1 = find_reg_equal_equiv_note (rinsn1);
   rtx note2 = find_reg_equal_equiv_note (rinsn2);
   if (note1 && note2 && rtx_equal_p (note1, note2))
-    return true;
+    {
+      /* REG_EQUIVs are invariant at function scope.  */
+      if (REG_NOTE_KIND (note2) == REG_EQUIV)
+       return true;
+
+      /* REG_EQUAL are not so in order to consider them similar the RTX they
+        point to must be identical.  We could also allow "rtx_equal"
+        REG_EQUALs but would need to check if no insn between them modifies
+        any of their sources.  */
+      return note1 == note2;
+    }
   return false;
 }
 
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c
 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c
new file mode 100644
index 00000000000..aeb337dc7ee
--- /dev/null
+++ 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-march=rv64gcv_zbb --param 
riscv-autovec-preference=fixed-vlmax" } */
+
+#include "multiple_rgroup-2.c"
+
+int main (void)
+{
+  TEST_ALL (run_1)
+  TEST_ALL (run_2)
+  TEST_ALL (run_3)
+  TEST_ALL (run_4)
+  TEST_ALL (run_5)
+  TEST_ALL (run_6)
+  TEST_ALL (run_7)
+  TEST_ALL (run_8)
+  TEST_ALL (run_9)
+  TEST_ALL (run_10)
+  return 0;
+}
-- 
2.41.0