Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

[Jeff Law]

On 11/13/23 07:47, Robin Dapp wrote:
As per Jeff's remark I'm going to push the attached.

Regards
  Robin

Subject: [PATCH v4] RISC-V: vsetvl: Refine REG_EQUAL equality.

This patch enhances the equality check for REG_EQUAL notes in the vsetvl
pass by using the == operator instead of rtx_equal_p.  With that, in
situations like the following, a5 and a7 are not considered equal
anymore.
One final note.  The register allocator tries to promote REG_EQUAL notes 
to REG_EQUIV notes when it's provably safe.  I don't think that code is 
terribly aggressive and I doubt it'd kick in for the forms shown below.


(insn 62 60 63 4 (set (reg:DI 17 a7 [orig:154 loop_len_54 ] [154])
         (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
             (reg:DI 30 t5 [219]))) 442 {umindi3}
      (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
             (const_int 8 [0x8]))
         (nil)))
(insn 63 62 65 4 (set (reg:DI 15 a5 [orig:175 _103 ] [175])
         (minus:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
             (reg:DI 17 a7 [orig:154 loop_len_54 ] [154]))) 11 {subdi3}
      (nil))
(insn 65 63 66 4 (set (reg:DI 16 a6 [orig:153 loop_len_53 ] [153])
         (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
             (reg:DI 30 t5 [219]))) 442 {umindi3}
      (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
             (const_int 8 [0x8]))
         (nil)))


Jeff