On Mon, Oct 2, 2023 at 7:10 AM Kito Cheng <kito.ch...@gmail.com> wrote:
>
> Just one nit and one more comment for doc:
>
> Could you add some doc something like that? mostly I grab from other
> target, so you can just included in the patch.
>
> diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
> index 31f2234640f..39396668da2 100644
> --- a/gcc/doc/install.texi
> +++ b/gcc/doc/install.texi
> @@ -1174,6 +1174,9 @@ Specify the default TLS dialect, for systems
> were there is a choice.
> For ARM targets, possible values for @var{dialect} are @code{gnu} or
> @code{gnu2}, which select between the original GNU dialect and the GNU TLS
> descriptor-based dialect.
> +For RISC-V targets, possible values for @var{dialect} are @code{trad} or
> +@code{desc}, which select between the traditional GNU dialect and the GNU TLS
> +descriptor-based dialect.
>
> @item --enable-multiarch
> Specify whether to enable or disable multiarch support. The default is
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 4085fc90907..459e266d426 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -1239,7 +1239,8 @@ See RS/6000 and PowerPC Options.
> -minline-atomics -mno-inline-atomics
> -minline-strlen -mno-inline-strlen
> -minline-strcmp -mno-inline-strcmp
> --minline-strncmp -mno-inline-strncmp}
> +-minline-strncmp -mno-inline-strncmp
> +-mtls-dialect=desc -mtls-dialect=trad}
>
> @emph{RL78 Options}
> @gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs
> @@ -29538,6 +29539,17 @@ which register to use as base register for
> reading the canary,
> and from what offset from that base register. There is no default
> register or offset as this is entirely for use within the Linux
> kernel.
> +
> +@opindex mtls-dialect=desc
> +@item -mtls-dialect=desc
> +Use TLS descriptors as the thread-local storage mechanism for dynamic
> accesses
> +of TLS variables. This is the default.
> +
> +@opindex mtls-dialect=trad
> +@item -mtls-dialect=traditional
-mtls-dialect=trad.
aarch64-linux-gnu-gcc doesn't support -mtls-dialect=traditional
> +Use traditional TLS as the thread-local storage mechanism for dynamic
> accesses
> +of TLS variables.
> +
> @end table
This is the default :)
I am happy that we change the default like AArch64, but probably not
now when linker support is not widely available yet.
I cannot comment on the code side as I am not familiar with GCC internals.
> @node RL78 Options
>
>
>
>
> > +(define_insn "@tlsdesc<mode>"
> > + [(set (reg:P A0_REGNUM)
> > + (unspec:P
> > + [(match_operand:P 0 "symbolic_operand" "")
> > + (match_operand:P 1 "const_int_operand")]
> > + UNSPEC_TLSDESC))
> > + (clobber (reg:SI T0_REGNUM))]
>
> P rather than SI here.
>
> > + "TARGET_TLSDESC"
> > + {
> > + return ".LT%1: auipc\ta0, %%tlsdesc_hi(%0)\;"
> > + "<load>\tt0,%%tlsdesc_load_lo(.LT%1)(a0)\;"
> > + "addi\ta0,a0,%%tlsdesc_add_lo(.LT%1)\;"
> > + "jalr\tt0,t0,%%tlsdesc_call(.LT%1)";
> > + }
> > + [(set_attr "type" "multi")
> > + (set_attr "length" "16")
> > + (set_attr "mode" "<MODE>")])
> > +
> > (define_insn "auipc<mode>"
> > [(set (match_operand:P 0 "register_operand" "=r")
> > (unspec:P
It seems that x86-64 supports non-adjacent code sequence. Writing the
pattern this way does not allow interleaving, but I assume
interleaving doesn't enable much.
https://reviews.llvm.org/D114416
--
宋方睿
