Hi Juzhe, Stage 3 will close today and there are still some patches that haven't been reviewed left. So is it possible to get xtheadvector merged in GCC-14? We emailed Kito regarding this, but haven't got any reply yet.
Joshua ------------------------------------------------------------------ 发件人：juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> 发送时间：2024年1月4日(星期四) 17:18 收件人："cooper.joshua"<cooper.jos...@linux.alibaba.com>; jeffreyalaw<jeffreya...@gmail.com>; "gcc-patches"<gcc-patches@gcc.gnu.org> 抄 送：Jim Wilson<jim.wilson....@gmail.com>; palmer<pal...@dabbelt.com>; andrew<and...@sifive.com>; "philipp.tomsich"<philipp.toms...@vrull.eu>; "christoph.muellner"<christoph.muell...@vrull.eu>; jinma<ji...@linux.alibaba.com>; "cooper.qu"<cooper...@linux.alibaba.com> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. \ No newline at end of file Each file needs newline. I am not able to review arch stuff. This needs kito. Besides, Andrew Pinski want us defer theadvector to GCC-15. I have no strong opinion here. juzhe.zh...@rivai.ai 发件人： joshua 发送时间： 2024-01-04 17:15 收件人： 钟居哲; Jeff Law; gcc-patches 抄送： jim.wilson.gcc; palmer; andrew; philipp.tomsich; Christoph Müllner; jinma; Cooper Qu 主题： Re：Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. Hi Juzhe, So is the following patch that this patch relies on OK to commit? https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html Joshua ------------------------------------------------------------------ 发件人：钟居哲 <juzhe.zh...@rivai.ai> 发送时间：2024年1月2日(星期二) 06:57 收件人：Jeff Law<jeffreya...@gmail.com>; "cooper.joshua"<cooper.jos...@linux.alibaba.com>; "gcc-patches"<gcc-patches@gcc.gnu.org> 抄 送："jim.wilson.gcc"<jim.wilson....@gmail.com>; palmer<pal...@dabbelt.com>; andrew<and...@sifive.com>; "philipp.tomsich"<philipp.toms...@vrull.eu>; "Christoph Müllner"<christoph.muell...@vrull.eu>; jinma<ji...@linux.alibaba.com>; Cooper Qu<cooper...@linux.alibaba.com> 主 题：Re: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. This is Ok from my side. But before commit this patch, I think we need this patch first: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html I will be back to work so I will take a look at other patches today. juzhe.zh...@rivai.ai From: Jeff Law Date: 2024-01-01 01:43 To: Jun Sha (Joshua); gcc-patches CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; christoph.muellner; juzhe.zhong; Jin Ma; Xianmiao Qu Subject: Re: [PATCH v4] RISC-V: Adds the prefix "th." for the instructions of XTheadVector. On 12/28/23 21:19, Jun Sha (Joshua) wrote: > This patch adds th. prefix to all XTheadVector instructions by > implementing new assembly output functions. We only check the > prefix is 'v', so that no extra attribute is needed. > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (riscv_asm_output_opcode): > New function to add assembler insn code prefix/suffix. > * config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise. > * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise. > > Co-authored-by: Jin Ma <ji...@linux.alibaba.com> > Co-authored-by: Xianmiao Qu <cooper...@linux.alibaba.com> > Co-authored-by: Christoph Müllner <christoph.muell...@vrull.eu> > --- > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv.cc | 14 ++++++++++++++ > gcc/config/riscv/riscv.h | 4 ++++ > .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 ++++++++++++ > 4 files changed, 31 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c > > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > index 31049ef7523..5ea54b45703 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -102,6 +102,7 @@ struct riscv_address_info { > }; > > /* Routines implemented in riscv.cc. */ > +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char > *p); > extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); > extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); > extern int riscv_float_const_rtx_index_for_fli (rtx); > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 0d1cbc5cb5f..ea1d59d9cf2 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5636,6 +5636,20 @@ riscv_get_v_regno_alignment (machine_mode mode) > return lmul; > } > > +/* Define ASM_OUTPUT_OPCODE to do anything special before > + emitting an opcode. */ > +const char * > +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) > +{ > + /* We need to add th. prefix to all the xtheadvector > + insturctions here.*/ > + if (TARGET_XTHEADVECTOR && current_output_insn != NULL_RTX && > + p[0] == 'v') > + fputs ("th.", asm_out_file); > + > + return p; Just a formatting nit. The GNU standards break lines before the operator, not after. So if (TARGET_XTHEADVECTOR && current_output_insn != NULL && p[0] == 'v') Note that current_output_insn is "extern rtx_insn *", so use NULL, not NULL_RTX. Neither of these nits require a new version for review. Just fix them. If Juzhe is fine with this, so am I. We can refine it if necessary later. jeff
