This is a follow-up to the previous patch to ensure that integer vector bit-masks do not have excess bits set. It fixes a bug, observed on amdgcn, in which the mask could be incorrectly set to zero, resulting in wrong-code.
The mask was broken when nunits==32. The patched version will probably be broken for nunits==64, but I don't think any current targets have masks with more than 64 bits. OK for mainline? Andrew gcc/ChangeLog: * expr.cc (store_constructor): Use 64-bit shifts. --- gcc/expr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/expr.cc b/gcc/expr.cc index e238811110e..90de5decee3 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -7879,7 +7879,7 @@ store_constructor (tree exp, rtx target, int cleared, poly_int64 size, auto nunits = TYPE_VECTOR_SUBPARTS (type).to_constant (); if (maybe_ne (GET_MODE_PRECISION (mode), nunits)) tmp = expand_binop (mode, and_optab, tmp, - GEN_INT ((1 << nunits) - 1), target, + GEN_INT ((1UL << nunits) - 1), target, true, OPTAB_WIDEN); if (tmp != target) emit_move_insn (target, tmp); -- 2.41.0