> Am 23.02.2024 um 14:03 schrieb Jakub Jelinek <ja...@redhat.com>:
>
> On Fri, Feb 23, 2024 at 12:58:53PM +0000, Andrew Stubbs wrote:
>> This is a follow-up to the previous patch to ensure that integer vector
>> bit-masks do not have excess bits set. It fixes a bug, observed on
>> amdgcn, in which the mask could be incorrectly set to zero, resulting in
>> wrong-code.
>>
>> The mask was broken when nunits==32. The patched version will probably
>> be broken for nunits==64, but I don't think any current targets have
>> masks with more than 64 bits.
>>
>> OK for mainline?
>>
>> Andrew
>>
>> gcc/ChangeLog:
>>
>> * expr.cc (store_constructor): Use 64-bit shifts.
>
> No, this isn't 64-bit shift on all hosts.
> Use HOST_WIDE_INT_1U instead.
I think there are now two other similar places recently added that need
adjustment as well.
Richard
>> --- a/gcc/expr.cc
>> +++ b/gcc/expr.cc
>> @@ -7879,7 +7879,7 @@ store_constructor (tree exp, rtx target, int cleared,
>> poly_int64 size,
>> auto nunits = TYPE_VECTOR_SUBPARTS (type).to_constant ();
>> if (maybe_ne (GET_MODE_PRECISION (mode), nunits))
>> tmp = expand_binop (mode, and_optab, tmp,
>> - GEN_INT ((1 << nunits) - 1), target,
>> + GEN_INT ((1UL << nunits) - 1), target,
>> true, OPTAB_WIDEN);
>> if (tmp != target)
>> emit_move_insn (target, tmp);
>> --
>> 2.41.0
>
> Jakub
>
